Single D-type flip-flop; positive-edge trigger

DESCRIPTION The 74LVC1G80 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. F

文件：99.43 Kbytes 页数：18 Pages

PANASONIC

松下

Single D-type flip-flop; positive-edge trigger

General description The 74LVC1G80 provides a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one set-up time prior to the LOW-to-HIGH clock transitio

文件：90.74 Kbytes 页数：16 Pages

恩XP

Single D-type flip-flop; positive-edge trigger

1. General description The 74LVC1G80 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output. Inputs can be drive

文件：277.35 Kbytes 页数：19 Pages

NEXPERIA

安世

Single D-type flip-flop; positive-edge trigger

Panasonic

松下

Single D-type flip-flop; positive-edge trigger

General description The 74LVC1G80 provides a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one set-up time prior to the LOW-to-HIGH clock transitio

文件：90.74 Kbytes 页数：16 Pages

恩XP

丝印：VT；Package：SOT886；Single D-type flip-flop; positive-edge trigger

1. General description The 74LVC1G80 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output. Inputs can be drive

文件：277.35 Kbytes 页数：19 Pages

NEXPERIA

安世

Single D-type flip-flop; positive-edge trigger

General description The 74LVC1G80 provides a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one set-up time prior to the LOW-to-HIGH clock transitio

文件：90.74 Kbytes 页数：16 Pages

恩XP

Single D-type flip-flop; positive-edge trigger

DESCRIPTION The 74LVC1G80 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. F

文件：99.43 Kbytes 页数：18 Pages

PANASONIC

松下

丝印：VT；Package：SOT1115；Single D-type flip-flop; positive-edge trigger

1. General description The 74LVC1G80 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output. Inputs can be drive

文件：277.35 Kbytes 页数：19 Pages

NEXPERIA

安世

丝印：VT；Package：SOT1202；Single D-type flip-flop; positive-edge trigger

1. General description The 74LVC1G80 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output. Inputs can be drive

文件：277.35 Kbytes 页数：19 Pages

NEXPERIA

安世