丝印：VG；Package：SOT1115；Single 2-input OR gate

1. General description The 74LVC1G32 is a single 2-input OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower inp

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NEXPERIA

安世

Single 2-input OR gate

General description The 74LVC1G32 is a single 2-input OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input ri

文件：282.32 Kbytes 页数：17 Pages

NEXPERIA

安世

Single 2-input OR gate

General description The 74LVC1G32 is a single 2-input OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input ri

文件：282.32 Kbytes 页数：17 Pages

NEXPERIA

安世

丝印：VG；Package：SOT1202；Single 2-input OR gate

1. General description The 74LVC1G32 is a single 2-input OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower inp

文件：255.33 Kbytes 页数：16 Pages

NEXPERIA

安世

丝印：V32；Package：SOT753；Single 2-input OR gate

1. General description The 74LVC1G32 is a single 2-input OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower inp

文件：255.33 Kbytes 页数：16 Pages

NEXPERIA

安世

丝印：V32；Package：SOT753；Single 2-input OR gate

General description The 74LVC1G32 is a single 2-input OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input ri

文件：282.32 Kbytes 页数：17 Pages

NEXPERIA

安世

Single 2-input OR gate

DESCRIPTION The 74LVC1G32 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply voltage range from 1.65 V to 5.5 V • High noise immunity • Complies with JEDEC standard: – JESD8-7 (1.65 V to 1.95

文件：84.68 Kbytes 页数：14 Pages

PANASONIC

松下

Single 2-input OR gate

General description The 74LVC1G32 provides one 2-input OR function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications. Schmitt trigger action at all inputs makes the circuit tolerant of slower i

文件：79.98 Kbytes 页数：14 Pages

恩XP

丝印：V32；Package：SC-74A；Single 2-input OR gate

1. General description The 74LVC1G32-Q100 is a single 2-input OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slowe

文件：217.28 Kbytes 页数：12 Pages

NEXPERIA

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丝印：V32；Package：SC-74A；Single 2-input OR gate

1. General description The 74LVC1G32-Q100 is a single 2-input OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slowe

文件：242.86 Kbytes 页数：14 Pages

NEXPERIA

安世