丝印：YT；Package：SOT1115；Single D-type flip-flop with reset; positive-edge trigger

1. General description The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the

文件：268.13 Kbytes 页数：17 Pages

NEXPERIA

安世

丝印：YT；Package：SOT1202；Single D-type flip-flop with reset; positive-edge trigger

1. General description The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the

文件：268.13 Kbytes 页数：17 Pages

NEXPERIA

安世

丝印：Y75；Package：SOT457；Single D-type flip-flop with reset; positive-edge trigger

1. General description The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the

文件：268.13 Kbytes 页数：17 Pages

NEXPERIA

安世

Single D-type flip-flop with reset; positive-edge trigger

General description The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the

文件：100.65 Kbytes 页数：17 Pages

恩XP

Single D-type flip-flop with reset; positive-edge trigger

General description The 74LVC1G175 is a high-performance, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. Th

文件：91.58 Kbytes 页数：17 Pages

PHI

PHI

Single D-type flip-flop with reset; positive-edge trigger

General description The 74LVC1G175 is a high-performance, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. Th

文件：91.58 Kbytes 页数：17 Pages

PHI

PHI

Single D-type flip-flop with reset; positive-edge trigger

General description The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the

文件：100.65 Kbytes 页数：17 Pages

恩XP

丝印：YT；Package：SOT363-2；Single D-type flip-flop with reset; positive-edge trigger

1. General description The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the

文件：268.13 Kbytes 页数：17 Pages

NEXPERIA

安世

SINGLE SCHMITT-TRIGGER BUFFER

Description The 74LVC1G17 is a single 1-input Schmitt-trigger buffer with a standard push-pull output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to 5.5V allowing this device to be used in a mixed voltage environment. The device is ful

文件：273.62 Kbytes 页数：14 Pages

DIODES

美台半导体

SINGLE SCHMITT-TRIGGER BUFFER

Description The 74LVC1G17 is a single 1-input Schmitt-trigger buffer with a standard push-pull output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to 5.5V allowing this device to be used in a mixed voltage environment. The device is ful

文件：273.62 Kbytes 页数：14 Pages

DIODES

美台半导体