74LVC126: Low-Voltage CMOS Quad Buffer, 3-State

The 74LVC126A is a high performance, non−inverting quad buffer operating from a 1.2 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VI specification of 5.5 V allows Designed for 1.2 to 3.6 V VCC Operation\n5.0 V Tolerant − Interface Capability With 5.0 V TTL Logic\nSupports Live Insertion and Withdrawal\nIOFF Specification Guarantees High Impedance When VCC = 0 V\n24 mA Output Sink and Source Capability\nNear Zero Static Supply Current in all Three Logic States;

ONSEMI

安森美半导体

Quad buffer/line driver with 5 V tolerant input/outputs; 3-state

1. General description The 74LVC126A is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A LOW on nOE causes the outputs to assume a high impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these

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Low-Voltage CMOS Quad 2-Input NAND Gate

Low-Voltage CMOS Quad Buffer With 5 V−Tolerant Inputs and Outputs (3−State, Non−Inverting) The 74LVC126A is a high performance, non−inverting quad buffer operating from a 1.2 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL comp

文件：101.89 Kbytes 页数：9 Pages

ONSEMI

安森美半导体

Quad buffer/line driver with 5 Volt tolerant input/outputs; 3-state

DESCRIPTION The 74LVC126A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 V. The 74LVC126A consists of four non-inver

文件：115.59 Kbytes 页数：20 Pages

PHI

PHI

QUADRUPLE 3-STATE BUFFERS

Description The 74LVC126A provides four independent buffers with three state outputs. Each output is independently controlled by an associated output enable pin (OE) which places the device in the high impedance state when driven low. The device is designed for operation with a power supply range

文件：230.22 Kbytes 页数：10 Pages

DIODES

美台半导体

Quad buffer/line driver with 5 Volt tolerant input/outputs; 3-state

DESCRIPTION The 74LVC126A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 V. The 74LVC126A consists of four non-inver

文件：115.59 Kbytes 页数：20 Pages

PHI

PHI

Quad buffer/line driver with 5 V tolerant input/outputs; 3-state

1. General description The 74LVC126A is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A LOW on nOE causes the outputs to assume a high impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these

文件：249.14 Kbytes 页数：13 Pages

NEXPERIA

安世

Quad buffer/line driver with 5 V tolerant input/outputs; 3-state

General description The 74LVC126A-Q100 consists of four non-inverting buffers/line drivers with 3-state outputs, which are controlled by the output enable input (nOE). A LOW at nOE causes the outputs to assume a high-impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. Whe

文件：236.2 Kbytes 页数：13 Pages

NEXPERIA

安世

Quad buffer/line driver with 5 Volt tolerant input/outputs; 3-state

DESCRIPTION The 74LVC126A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 V. The 74LVC126A consists of four non-inver

文件：115.59 Kbytes 页数：20 Pages

PHI

PHI

Quad buffer/line driver with 5 V tolerant input/outputs; 3-state

1. General description The 74LVC126A is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A LOW on nOE causes the outputs to assume a high impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these

文件：249.14 Kbytes 页数：13 Pages

NEXPERIA

安世