Triple 2-channel analog multiplexer/demultiplexer

DESCRIPTION The 74LV4053 is a low-voltage CMOS device and is pin and function compatible with the 74HC/HCT4053. FEATURES •Optimized for low voltage applications: 1.0 to 6.0 V •Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V •Low typ “ON” resistance: 100 at Vcc– VE

文件：154.89 Kbytes 页数：16 Pages

PHI

PHI

Triple single-pole double-throw analog switch

General description The 74LV4053 is a triple single-pole double-throw (SPDT) analog switch, suitable for use as an analog or digital multiplexer/demultiplexer. It is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC4053 and 74HCT4053. Each switch has a digital s

文件：162.77 Kbytes 页数：26 Pages

恩XP

Triple single-pole double-throw analog switch

1. General description The 74LV4053 is a triple single-pole double-throw (SPDT) analog switch, suitable for use in 2:1 multiplexer/demultiplexer applications. Each switch features a digital select input (Sn), two independent inputs/outputs (Y0 and Y1) and a common input/output (Z). A digital en

文件：335.89 Kbytes 页数：20 Pages

NEXPERIA

安世

Triple single-pole double-throw analog switch

General description The 74LV4053 is a triple single-pole double-throw (SPDT) analog switch, suitable for use as an analog or digital multiplexer/demultiplexer. It is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC4053 and 74HCT4053. Each switch has a digital s

文件：162.77 Kbytes 页数：26 Pages

恩XP

Triple 2-channel analog multiplexer/demultiplexer

DESCRIPTION The 74LV4053 is a low-voltage CMOS device and is pin and function compatible with the 74HC/HCT4053. FEATURES •Optimized for low voltage applications: 1.0 to 6.0 V •Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V •Low typ “ON” resistance: 100 at Vcc– VE

文件：154.89 Kbytes 页数：16 Pages

PHI

PHI

Triple single-pole double-throw analog switch

文件：782.99 Kbytes 页数：25 Pages

NEXPERIA

安世

Triple single-pole double-throw analog switch

The 74LV4053 is a triple single-pole double-throw (SPDT) analog switch, suitable for use as an analog or digital multiplexer/demultiplexer. It is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC4053 and 74HCT4053. Each switch has a digital select input (Sn), two ind • Optimized for low-voltage applications: 1.0 V to 3.6 V\n• Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V\n• Low ON resistance:• 180 Ω (typical) at VCC - VEE = 2.0 V\n• 100 Ω (typical) at VCC - VEE = 3.0 V\n• 75 Ω (typical) at VCC - VEE = 4.5 V\n\n• Logic level translation:• To enable;

Nexperia

安世

Triple single-pole double-throw analog switch

The 74LV4053 is a triple single-pole double-throw (SPDT) analog switch, suitable for use as an analog or digital multiplexer/demultiplexer. It is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC4053 and 74HCT4053. Each switch has a digital select input (Sn), two ind • Optimized for low-voltage applications: 1.0 V to 3.6 V\n• Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V\n• Low ON resistance:• 180 Ω (typical) at VCC - VEE = 2.0 V\n• 100 Ω (typical) at VCC - VEE = 3.0 V\n• 75 Ω (typical) at VCC - VEE = 4.5 V\n\n• Logic level translation:• To enable;

Nexperia

安世

Triple single-pole double-throw analog switch

The 74LV4053-Q100 is a triple single-pole double-throw (SPDT) analog switch, suitable for use as an analog or digital multiplexer/demultiplexer. It is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC4053-Q100 and 74HCT4053-Q100. Each switch has a digital select inpu • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from ‑40 °C to +85 °C and from ‑40 °C to +125 °C\n\n• Optimized for low-voltage applications: 1.0 V to 3.6 V\n• Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V\n• Low ON resistance:• 180 Ω (typical) at V;

Nexperia

安世