74LV4053D中文资料安世数据手册PDF规格书

1. General description

The 74LV4053 is a triple single-pole double-throw (SPDT) analog switch, suitable for use in

2:1 multiplexer/demultiplexer applications. Each switch features a digital select input (Sn), two

independent inputs/outputs (Y0 and Y1) and a common input/output (Z). A digital enable input (E)

is common to all switches. When E is HIGH, the switches are turned off.

Digital inputs include clamp diodes. This enables the use of current limiting resistors to interface

inputs to voltages in excess VCC.

2. Features and benefits

• Wide supply voltage range from 1.0 V to 6.0 V

• Optimized for low-voltage applications: 1.0 V to 3.6 V

• CMOS low power disssipation

• Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V

• Low ON resistance:

• 180 Ω (typical) at VCC - VEE = 2.0 V

• 100 Ω (typical) at VCC - VEE = 3.0 V

• 75 Ω (typical) at VCC - VEE = 4.5 V

• Logic level translation:

• To enable 3 V logic to communicate with ±3 V analog signals

• Typical ‘break before make’ built in

• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

• Complies with JEDEC standards:

• JESD8-7 (1.65 V to 1.95 V)

• JESD8-5 (2.3 V to 2.7 V)

• JESD8C (2.7 V to 3.6 V)

• JESD36 (4.6 V to 5.5 V)

• ESD protection:

• HBM JESD22-A114-C exceeds 2000 V

• MM JESD22-A115-A exceeds 200 V

• Multiple package options

• Specified from -40 °C to +85 °C and from -40 °C to +125 °C