3-to-8 line decoder/multiplexer; inverting

DESCRIPTION The 74LV138 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT138. The 74LV138 accepts three binary weighted address inputs (A0, A1, A2) and when enabled, provide 8 mutually exclusive active LOW outputs (Y0 to Y7). FEATURES • Wide operatin

文件：116.32 Kbytes 页数：12 Pages

PHI

PHI

3-to-8 line decoder/demultiplexer; inverting

General description The 74LV138 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC138 and 74HCT138. The 74LV138 is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted address inputs (A0, A1 and A2) and, when enabled, provides eight mutually excl

文件：105.33 Kbytes 页数：17 Pages

恩XP

3-to-8 line decoder/demultiplexer; inverting

1. General description The 74LV138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The 74LVC138A features three enable inputs (Y1, Y2 and E3). Every output will be HIGH unless Y1 and Y2 are LOW and E3 is HIGH. This multiple enable fun

文件：256.18 Kbytes 页数：14 Pages

NEXPERIA

安世

3-to-8 line decoder/multiplexer; inverting

DESCRIPTION The 74LV138 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT138. The 74LV138 accepts three binary weighted address inputs (A0, A1, A2) and when enabled, provide 8 mutually exclusive active LOW outputs (Y0 to Y7). FEATURES • Wide operatin

文件：116.32 Kbytes 页数：12 Pages

PHI

PHI

3-to-8 line decoder/demultiplexer; inverting

General description The 74LV138 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC138 and 74HCT138. The 74LV138 is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted address inputs (A0, A1 and A2) and, when enabled, provides eight mutually excl

文件：105.33 Kbytes 页数：17 Pages

恩XP

3-to-8 line decoder/multiplexer; inverting

DESCRIPTION The 74LV138 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT138. The 74LV138 accepts three binary weighted address inputs (A0, A1, A2) and when enabled, provide 8 mutually exclusive active LOW outputs (Y0 to Y7). FEATURES • Wide operatin

文件：116.32 Kbytes 页数：12 Pages

PHI

PHI

3-to-8 line decoder/demultiplexer; inverting

文件：113.24 Kbytes 页数：17 Pages

PHI

PHI

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

文件：649.05 Kbytes 页数：18 Pages

TI

德州仪器

丝印：74LV138A；Package：SO；3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

FEATURES · 2-V to 5.5-V VCC Operation · Max t pd of 9.5 ns at 5 V · Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 3.3 V, TA = 25°C · Support Mixed-Mode Voltage Operation on All Ports · Ioff Supports Partial-Pow

文件：1.85981 Mbytes 页数：33 Pages

TI

德州仪器

3-to-8 line decoder/demultplexer; inverting

The 74LV138 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC138 and 74HCT138.\n The 74LV138 is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted address inputs (A0, A1 and A2) and, when enabled, provides eight mutually exclusive active LOW out • Wide operating voltage: 1.0 V to 5.5 V\n• Optimized for low voltage applications: 1.0 V to 3.6 V\n• Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V\n• Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C\n• Typical HIGH-level output voltage (VOH) undershoot: > 2 V at V;

Nexperia

安世