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型号	下载订购	功能描述	制造商上传企业	LOGO
74LV138	文件：116.32 Kbytes Page：12 Pages	3-to-8 line decoder/multiplexer; inverting DESCRIPTION The 74LV138 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT138. The 74LV138 accepts three binary weighted address inputs (A0, A1, A2) and when enabled, provide 8 mutually exclusive active LOW outputs (Y0 to Y7). FEATURES • Wide operatin 文件：116.32 Kbytes 页数：12 Pages	PHI PHI	PHI
74LV138	文件：105.33 Kbytes Page：17 Pages	3-to-8 line decoder/demultiplexer; inverting General description The 74LV138 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC138 and 74HCT138. The 74LV138 is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted address inputs (A0, A1 and A2) and, when enabled, provides eight mutually excl 文件：105.33 Kbytes 页数：17 Pages	恩XP	恩XP
74LV138	文件：256.18 Kbytes Page：14 Pages	3-to-8 line decoder/demultiplexer; inverting 1. General description The 74LV138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The 74LVC138A features three enable inputs (Y1, Y2 and E3). Every output will be HIGH unless Y1 and Y2 are LOW and E3 is HIGH. This multiple enable fun 文件：256.18 Kbytes 页数：14 Pages	NEXPERIA 安世	NEXPERIA
74LV138BQ	文件：256.18 Kbytes Page：14 Pages	3-to-8 line decoder/demultiplexer; inverting 1. General description The 74LV138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The 74LVC138A features three enable inputs (Y1, Y2 and E3). Every output will be HIGH unless Y1 and Y2 are LOW and E3 is HIGH. This multiple enable fun 文件：256.18 Kbytes 页数：14 Pages	NEXPERIA 安世	NEXPERIA
74LV138BQ	文件：105.33 Kbytes Page：17 Pages	3-to-8 line decoder/demultiplexer; inverting General description The 74LV138 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC138 and 74HCT138. The 74LV138 is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted address inputs (A0, A1 and A2) and, when enabled, provides eight mutually excl 文件：105.33 Kbytes 页数：17 Pages	恩XP	恩XP
74LV138D	文件：105.33 Kbytes Page：17 Pages	3-to-8 line decoder/demultiplexer; inverting General description The 74LV138 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC138 and 74HCT138. The 74LV138 is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted address inputs (A0, A1 and A2) and, when enabled, provides eight mutually excl 文件：105.33 Kbytes 页数：17 Pages	恩XP	恩XP
74LV138D	文件：256.18 Kbytes Page：14 Pages	3-to-8 line decoder/demultiplexer; inverting 1. General description The 74LV138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The 74LVC138A features three enable inputs (Y1, Y2 and E3). Every output will be HIGH unless Y1 and Y2 are LOW and E3 is HIGH. This multiple enable fun 文件：256.18 Kbytes 页数：14 Pages	NEXPERIA 安世	NEXPERIA
74LV138D	文件：116.32 Kbytes Page：12 Pages	3-to-8 line decoder/multiplexer; inverting DESCRIPTION The 74LV138 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT138. The 74LV138 accepts three binary weighted address inputs (A0, A1, A2) and when enabled, provide 8 mutually exclusive active LOW outputs (Y0 to Y7). FEATURES • Wide operatin 文件：116.32 Kbytes 页数：12 Pages	PHI PHI	PHI
74LV138DB	文件：116.32 Kbytes Page：12 Pages	3-to-8 line decoder/multiplexer; inverting DESCRIPTION The 74LV138 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT138. The 74LV138 accepts three binary weighted address inputs (A0, A1, A2) and when enabled, provide 8 mutually exclusive active LOW outputs (Y0 to Y7). FEATURES • Wide operatin 文件：116.32 Kbytes 页数：12 Pages	PHI PHI	PHI
74LV138DB	文件：105.33 Kbytes Page：17 Pages	3-to-8 line decoder/demultiplexer; inverting General description The 74LV138 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC138 and 74HCT138. The 74LV138 is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted address inputs (A0, A1 and A2) and, when enabled, provides eight mutually excl 文件：105.33 Kbytes 页数：17 Pages	恩XP	恩XP

技术参数

VCC (V)：
1.0 - 5.5
Logic switching levels：
TTL
Output drive capability (mA)：
± 12
tpd (ns)：
12
Power dissipation considerations：
low
Tamb (°C)：
-40~125
Rth(j-a) (K/W)：
83
Ψth(j-top) (K/W)：
6.5
Rth(j-c) (K/W)：
50
Package name：
DHVQFN16

供应商	型号	品牌	批号	封装	库存	备注	价格
芯有半导体（深圳）有限公司	74LV138	PHI	00+	TSSOP16	3544	全新原装100真实现货供应	询价
深圳市福安瓯科技有限公司	74LV138	PHI	25+	TSSOP16	9531	⊙⊙新加坡大量现货库存,深圳常备现货!欢迎查询!⊙	询价
深圳市豪迈兴电子有限公司	74LV138	PHI	24+	TSSOP16	21322	公司原厂原装现货假一罚十!特价出售!强势库存!	询价
深圳市一线半导体有限公司	74LV138		24+		5000	公司存货	询价
深圳市佳鑫美电子科技有限公司	74LV138	PHI	25+	TSSOP16	2987	只售原装自家现货!诚信经营!欢迎来电!	询价
千层芯半导体(深圳)有限公司	74LV138	Nexperia	24+	TSSOP-16	50000	一级代理进口原装现货假一赔十	询价
深圳市亿智腾科技有限公司	74LV138	PHI	24+	TSSOP16	6540	原装现货/欢迎来电咨询	询价
深圳庞田科技有限公司	74LV138	FAIRCHILD	2023+环保现货	TSSOP	4425	专注军工、汽车、医疗、工业等方案配套一站式服务	询价
深圳市亚泰盈科电子有限公司	74LV138	TI	25+	SOP5.2	2000	全新现货	询价
深圳市联世界科技有限公司	74LV138DB	PHI	24+/25+		1200	原装正品现货库存价优	询价

更多74LV138供应商更新时间2026-1-17 10:32:00

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