Triple 3-Input AND Gate

General Description This device contains three independent gates each of which performs the logic AND function. Features ■ Alternate military/aerospace device (54LS11) is available. Contact a National Semiconductor Sales Office/Distributor for specifications.

文件：46.02 Kbytes 页数：4 Pages

Fairchild

仙童半导体

TRIPLE 3-INPUT AND GATE

TRIPLE 3-INPUT AND GATE

文件：56.62 Kbytes 页数：1 Pages

ETCList of Unclassifed Manufacturers

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Triple 3-Input AND Gate

General Description This device contains three independent gates each of which performs the logic AND function.

文件：93.18 Kbytes 页数：4 Pages

SYC

Triple 3-Input AND Gate

7411, 74LS11, DM74LS11 Datasheet.\n\nThis device contains three independent gates each of which performs the logic AND function.

ONSEMI

安森美半导体

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs

General Description This device contains two independent negative-edge-trig gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra

文件：52 Kbytes 页数：5 Pages

Fairchild

仙童半导体

Dual J-K Negative-edge-triggered Flip-Flops(with Preset and Clear)

● Quadrupie 2-Input Positive NAND Gates ● Quadruple 2-Input Positive NAND Gates (with Open Collector Output) (Continue....)

文件：76.76 Kbytes 页数：7 Pages

HitachiHitachi Semiconductor

日立日立公司

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

The SN54 /74LS112A dual JKflip-flop features individual J, K, clock, and asynchronousset and clear inputs to each flip-flop. When the clock goes HIGH,the inputs are enabled and data will be accepted. The logic level of the Jand K inputs may be allowed to change when the clock pulse is HIGH and the

文件：147.33 Kbytes 页数：4 Pages

Motorola

摩托罗拉

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs

General Description This device contains two independent negative-edge-trig gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra

文件：52 Kbytes 页数：5 Pages

Fairchild

仙童半导体

TRIPLE 3-INPUT AND GATE

TRIPLE 3-INPUT AND GATE

文件：56.62 Kbytes 页数：1 Pages

ETCList of Unclassifed Manufacturers

未分类制造商

TRIPLE 3-INPUT AND GATE

TRIPLE 3-INPUT AND GATE

文件：56.62 Kbytes 页数：1 Pages

ETCList of Unclassifed Manufacturers

未分类制造商