Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs

General Description This device contains two independent negative-edge-trig gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra

文件：52 Kbytes 页数：5 Pages

Fairchild

仙童半导体

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

文件：147.21 Kbytes 页数：4 Pages

Motorola

摩托罗拉

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs

General Description This device contains two independent negative-edge-trig gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra

文件：52 Kbytes 页数：5 Pages

Fairchild

仙童半导体

DUAL NEGATIVE-EDGE-TRIGERED MASTER-SLAVE J-K FLIP-FLOPS WITH PRESET, CLEAR, AND COMPLEMENTARY OUTPUTS

文件：102.78 Kbytes 页数：3 Pages

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

DUAL NEGATIVE-EDGE-TRIGERED MASTER-SLAVE J-K FLIP-FLOPS WITH PRESET, CLEAR, AND COMPLEMENTARY OUTPUTS

文件：102.78 Kbytes 页数：3 Pages

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司