SN74LS112D数据手册供应代理摩托罗拉-114ic电子网

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型号	下载订购	功能描述	制造商上传企业	LOGO
SN74LS112D	文件：147.33 Kbytes Page：4 Pages	DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 /74LS112A dual JKflip-flop features individual J, K, clock, and asynchronousset and clear inputs to each flip-flop. When the clock goes HIGH,the inputs are enabled and data will be accepted. The logic level of the Jand K inputs may be allowed to change when the clock pulse is HIGH and the 文件：147.33 Kbytes 页数：4 Pages	Motorola 摩托罗拉	Motorola
SN74LS112D	文件：300.4 Kbytes Page：9 Pages	DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR 文件：300.4 Kbytes 页数：9 Pages	TI 德州仪器	TI
SN74LS112N	文件：300.4 Kbytes Page：9 Pages	DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR 文件：300.4 Kbytes 页数：9 Pages	TI 德州仪器	TI
SN74LS112N	文件：147.33 Kbytes Page：4 Pages	DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 /74LS112A dual JKflip-flop features individual J, K, clock, and asynchronousset and clear inputs to each flip-flop. When the clock goes HIGH,the inputs are enabled and data will be accepted. The logic level of the Jand K inputs may be allowed to change when the clock pulse is HIGH and the 文件：147.33 Kbytes 页数：4 Pages	Motorola 摩托罗拉	Motorola

更多SN74LS112D供应商更新时间2025-10-4 16:01:00