Dual D-type flip-flop with set and reset; positive edge-trigger

文件：175.47 Kbytes 页数：21 Pages

PHI

PHI

Dual D-type flip-flop with set and reset; positive edge-trigger

文件：193.4 Kbytes 页数：22 Pages

PHI

PHI

Dual D-type flip-flop with set and reset; positive edge-trigger

文件：798.65 Kbytes 页数：19 Pages

NEXPERIA

安世

Dual D-type flip-flop with set and reset; positive edge-trigger

文件：798.65 Kbytes 页数：19 Pages

NEXPERIA

安世

Dual D-type flip-flop with set and reset; positive-edge trigger

The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition, is • Input levels:• For 74HC74: CMOS level\n• For 74HCT74: TTL level\n\n• Symmetrical output impedance\n• Low power dissipation\n• High noise immunity\n• Balanced propagation delays\n• Specified in compliance with JEDEC standard no. 7A\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A1;

Nexperia

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Dual D-type flip-flop with set and reset; positive-edge trigger

The 74HC74-Q100; 74HCT74-Q100 are dual positive edge triggered D-type flip-flop with individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition, w • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Input levels:• For 74HC74-Q100: CMOS level\n• For 74HCT74-Q100: TTL level\n\n• Symmetrical output impedance\n• Low power dissipation\n• High noise immunity\n• Bal;

Nexperia

安世

Dual D-type flip-flop with set and reset; positive edge-trigger

The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition, is • Wide supply voltage range from 2.0 to 6.0 V\n• CMOS low power dissipation\n• High noise immunity\n• Input levels:• For 74HC74: CMOS level\n• For 74HCT74: TTL level\n\n• Symmetrical output impedance\n• High noise immunity\n• Balanced propagation delays\n• Latch-up performance exceeds 100 mA per JES;

Nexperia

安世

Package：14-VFQFN 裸露焊盘；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 功能：设置（预设）和复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE DUAL 1BIT 14DHVQFN

Nexperia USA Inc.

Package：14-SOIC（0.154"，3.90mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 功能：设置（预设）和复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE DUAL 1BIT 14SO

Nexperia USA Inc.

Package：14-SOIC（0.154"，3.90mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 功能：设置（预设）和复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE DUAL 1BIT 14SO

Nexperia USA Inc.