74HCT74BZ

Dual D-type flip-flop with set and reset; positive edge-trigger

1.Generaldescription The74HC74and74HCT74aredualpositiveedgetriggeredD-typeflip-flop.Theyhaveindividual data(nD),clock(nCP),set(nSD)andreset(nRD)inputs,andcomplementarynQandnQoutputs. DataatthenD-input,thatmeetstheset-upandholdtimerequirementsontheLOW-

74HCT74BZ

Dual D-type flip-flop with set and reset; positive edge-trigger; • Wide supply voltage range from 2.0 to 6.0 V\n• CMOS low power dissipation\n• High noise immunity\n• Input levels:• For 74HC74: CMOS level\n• For 74HCT74: TTL level\n\n• Symmetrical output impedance\n• High noise immunity\n• Balanced propagation delays\n• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B\n• Complies with JEDEC standards:• JESD8C (2.7 V to 3.6 V)\n• JESD7A (2.0 V to 6.0 V)\n\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n• Multiple package options\n• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n;

The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition, is stored in the flip-flop and appears at the nQ output. Schmitt-trigger action in the clock input, makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.\n

74HCT74D

DualD-typeflip-flopwithsetandreset;positive-edgetrigger

GENERALDESCRIPTION The74HC/HCT74arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. FEATURES •Outputcapability:standard •ICCcategory:flip-flops

PHI

74HCT74D

DualD-typeflip-flopwithsetandreset;positiveedge-trigger

PHI

74LCX04MX

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