| 型号 | 下载 订购 | 功能描述 | 制造商 上传企业 | LOGO |
|---|---|---|---|---|
74HCT107 | Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc 文件：53.67 Kbytes 页数：7 Pages | PHI 飞利浦 | PHI | |
74HCT107 | Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J 文件：259.73 Kbytes 页数：15 Pages | NEXPERIANexperia B.V. All rights reserved 安世安世半导体(中国)有限公司 | NEXPERIA | |
Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J 文件：259.73 Kbytes 页数：15 Pages | NEXPERIANexperia B.V. All rights reserved 安世安世半导体(中国)有限公司 | NEXPERIA | ||
Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc 文件：53.67 Kbytes 页数：7 Pages | PHI 飞利浦 | PHI | ||
Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc 文件：53.67 Kbytes 页数：7 Pages | PHI 飞利浦 | PHI | ||
Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock inp 文件：259.39 Kbytes 页数：15 Pages | NEXPERIANexperia B.V. All rights reserved 安世安世半导体(中国)有限公司 | NEXPERIA | ||
Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc 文件：53.67 Kbytes 页数：7 Pages | PHI 飞利浦 | PHI | ||
Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc 文件：53.67 Kbytes 页数：7 Pages | PHI 飞利浦 | PHI | ||
Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock inp 文件：259.39 Kbytes 页数：15 Pages | NEXPERIANexperia B.V. All rights reserved 安世安世半导体(中国)有限公司 | NEXPERIA | ||
Dual JK flip-flop with reset; negative-edge trigger 文件：747.99 Kbytes 页数：17 Pages | NEXPERIANexperia B.V. All rights reserved 安世安世半导体(中国)有限公司 | NEXPERIA |
技术参数
- VCC (V)：
4.5 - 5.5
- Logic switching levels：
TTL
- Output drive capability (mA)：
± 4
- tpd (ns)：
16
- fmax (MHz)：
73
- Power dissipation considerations：
low
- Tamb (°C)：
-40~125
- Rth(j-a) (K/W)：
87
- Ψth(j-top) (K/W)：
6.5
- Rth(j-c) (K/W)：
45
- Package name：
SO14
| 供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
24+ |
5000 |
公司存货 |
询价 | ||||
ELCAP |
23+ |
DIP14 |
6000 |
原装正品假一罚百!可开增票! |
询价 | ||
HAR |
23+ |
NA |
20000 |
全新原装假一赔十 |
询价 | ||
PHI |
24+/25+ |
100 |
原装正品现货库存价优 |
询价 | |||
恩XP |
24+ |
N/A |
25843 |
公司原厂原装现货假一罚十!特价出售!强势库存! |
询价 | ||
ph |
24+ |
N/A |
6980 |
原装现货,可开13%税票 |
询价 | ||
恩XP |
18+ |
DIP14 |
85600 |
保证进口原装可开17%增值税发票 |
询价 | ||
PHI |
24+ |
SOP14 |
20000 |
全新原厂原装，进口正品现货，正规渠道可含税！！ |
询价 | ||
恩XP |
24+ |
N/A |
6540 |
原装现货/欢迎来电咨询 |
询价 | ||
PHI |
23+ |
SOP14 |
30000 |
代理全新原装现货,价格优势 |
询价 |
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