Dual JK flip-flop with reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc

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PHI

PHI

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：56.86 Kbytes 页数：8 Pages

TI

德州仪器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：451.69 Kbytes 页数：15 Pages

TI

德州仪器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：624.14 Kbytes 页数：16 Pages

TI

德州仪器