74HC590PW

8-bit binary counter with output register; 3-state

Generaldescription The74HC590isahigh-speedSi-gateCMOSdeviceandispincompatiblewithLowpowerSchottkyTTL(LSTTL).ItisspecifiedincompliancewithJEDECstandardno.7A. The74HC590isan8-bitbinarycounterwithastorageregisterand3-stateoutputs.Thestorageregisterhaspa

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74HC590PW

8-bit binary counter with output register; 3-state

1.Generaldescription The74HC590isan8-bitbinarycounterwithastorageregisterand3-stateoutputs.Thestorage registerhasparallel(Q0toQ7)outputs.Thebinarycounterfeaturesmasterresetcounter(MRC) andcountenable(CE)inputs.Thecounterandstorageregisterhaveseparatepo

74HC590PW

8-bit binary counter with output register; 3-state; • Counter and register have independent clock inputs\n• Counter has master reset\n• Complies with JEDEC standard no. 7A\n• Multiple package options\n• Input levels:• For 74HC590: CMOS level\n\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n• CDM JESD22-C101C exceeds 2000 V\n\n• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n;

The 74HC590 is an 8-bit binary counter with a storage register and 3-state outputs. The storage register has parallel (Q0 to Q7) outputs. The binary counter features master reset counter (MRC) and count enable (CE) inputs. The counter and storage register have separate positive edge triggered clock (CPC and CPR) inputs. If both clocks are connected together, the counter state is always one count ahead of the register. Internal circuitry prevents clocking from the clock enable. A ripple carry output (RCO) is provided for cascading. Cascading is accomplished by connecting RCO of the first stage to CE of the second stage. Cascading for larger count chains can be accomplished by connecting RCO of each stage to the counter clock (CPC) input of the following stage. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.\n

74HC590PW-Q100

8-bit binary counter with output register; 3-state;

The 74HC590-Q100 is an 8-bit binary counter with a storage register and 3-state outputs. The storage register has parallel (Q0 to Q7) outputs. The binary counter features master reset counter (MRC) and count enable (CE) inputs. The counter and storage register have separate positive edge triggered clock (CPC and CPR) inputs. If both clocks are connected together, the counter state is always one count ahead of the register. Internal circuitry prevents clocking from the clock enable. A ripple carry output (RCO) is provided for cascading. Cascading is accomplished by connecting RCO of the first stage to CE of the second stage. Cascading for larger count chains can be accomplished by connecting RCO of each stage to the counter clock (CPC) input of the following stage. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.\n This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.\n

74HC590PW,112

Package：16-TSSOP（0.173"，4.40mm 宽）；包装：管件 类别：集成电路（IC） 计数器，除法器 描述：IC COUNTER 8BIT BINARY 16-TSSOP

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74HC590PW,118

Package：16-TSSOP（0.173"，4.40mm 宽）；包装：管件 类别：集成电路（IC） 计数器，除法器 描述：IC COUNTER 8BIT BINARY 16-TSSOP

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