1. General description

The 74HC590 is an 8-bit binary counter with a storage register and 3-state outputs. The storage

register has parallel (Q0 to Q7) outputs. The binary counter features master reset counter (MRC)

and count enable (CE) inputs. The counter and storage register have separate positive edge

triggered clock (CPC and CPR) inputs. If both clocks are connected together, the counter state is

always one count ahead of the register. Internal circuitry prevents clocking from the clock enable.

A ripple carry output (RCO) is provided for cascading. Cascading is accomplished by connecting

RCO of the first stage to CE of the second stage. Cascading for larger count chains can be

accomplished by connecting RCO of each stage to the counter clock (CPC) input of the following

stage. Inputs include clamp diodes. This enables the use of current limiting resistors to interface

inputs to voltages in excess of VCC.

2. Features and benefits

• Wide supply voltage range from 2.0 V to 6.0 V

• CMOS low power dissipation

• High noise immunity

• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

• Complies with JEDEC standards:

• JESD8C (2.7 V to 3.6 V)

• JESD7A (2.0 V to 6.0 V)

• CMOS input levels

• Counter and register have independent clock inputs

• Counter has master reset

• Multiple package options

• ESD protection:

• HBM JESD22-A114F exceeds 2000 V

• MM JESD22-A115-A exceeds 200 V

• CDM JESD22-C101C exceeds 1000 V

• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

74HC590PW属于集成电路（IC） > 计数器，除法器。安世半导体(中国)有限公司制造生产的74HC590PW计数器，除法器计数器和除法器 IC 是数字逻辑器件，可对输入发生的逻辑转换进行计数，然后使用多个并行输出重新发送累加的计数，和/或生成单个输出信号转换，从而对应用某些整数数量输入信号转换进行响应。除了简单的事件计数，它们还可用于各种频率合成应用。