8-bit addressable latch

文件：174.08 Kbytes 页数：23 Pages

恩XP

8-bit addressable latch

文件：174.08 Kbytes 页数：23 Pages

恩XP

丝印：74HC259Y；Package：SO16(automotivegrade)；8-bit addressable latch

Features • High speed: tPD = 20 ns (typ.) at VCC = 6 V • Low power dissipation: ICC = 4 μA (max.) at TA = 25 °C • High noise immunity: VNIH = VNIL = 28 % VCC (min.) • Symmetrical output impedance: |IOH| = IOL = 4 mA (min) • Balanced propagation delays: tPLH ~= tPHL • Wide operating volta

文件：684.36 Kbytes 页数：19 Pages

STMICROELECTRONICS

意法半导体

8-bit addressable latch

The 74HC259-Q100; 74HCT259-Q100 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A.\n The 74HC259-Q100; 74HCT259-Q100 are high-speed 8-bit addressable latches designed for general-purpose stor • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Combined demultiplexer and 8-bit latch\n• Serial-to-parallel capability\n• Output from each storage bit available\n• Random (addressable) data entry\n• Easily exp;

Nexperia

安世

8-bit addressable latch

The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs A0 to A3. The addressed latch will follow the data input, non-addressed latches will retain their pre • Wide supply voltage range from 2.0 V to 6.0 V\n• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B\n• Complies with JEDEC standards:• JESD8C (2.7 V to 3.6 V)\n• JESD7A (2.0 V to 6.0 V)\n\n• Combined demultiplexer and 8-bit latch\n• Serial-to-parallel capability\n• Output from each s;

Nexperia

安世

8-bit addressable latch

The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs AO to A3. The addressed latch will follow the data input, non-addressed latches will retain their pre • Combined demultiplexer and 8-bit latch\n• Serial-to-parallel capability\n• Output from each storage bit available\n• Random (addressable) data entry\n• Easily expandable\n• Common reset input\n• Useful as a 3-to-8 active HIGH decoder\n• Complies with JEDEC standard no. 7A\n• Input levels:• For 74H;

Nexperia

安世

Package：16-VFQFN 裸露焊盘；包装：管件 类别：集成电路（IC） 锁存器 描述：IC LATCH 8BIT ADDRESS 16DHVQFN

Nexperia USA Inc.

Package：16-SOIC（0.154"，3.90mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 锁存器 描述：IC 8BIT ADDRESSABLE LATCH 16SOIC

Toshiba Semiconductor and Storage

Package：16-SOIC（0.154"，3.90mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 锁存器 描述：IC ADDRESSABLE LATCH 8BIT 16SOIC

Nexperia USA Inc.