8-bit addressable latch

GENERAL DESCRIPTION The 74HC/HCT259 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Combines demultiplexer and 8-bit latch • Serial-to-parallel capability • Outp

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PHI

飞利浦

8-bit addressable latch

General description The 74HC259; 74HCT259 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7-A.

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恩XP

8-bit addressable latch

1. General description The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs A0 to A3. The addressed latch will follow the data input, non-addressed l

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NEXPERIA

安世

8-bit addressable latch

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恩XP

8-bit addressable latch

General description The 74HC259-Q100; 74HCT259-Q100 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A.

文件：261.35 Kbytes 页数：20 Pages

恩XP

8-bit addressable latch

1. General description The 74HC259-Q100; 74HCT259-Q100 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs A0 to A3. The addressed latch will follow the data input, non-a

文件：287.38 Kbytes 页数：17 Pages

NEXPERIA

安世

8-bit addressable latch

The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs AO to A3. The addressed latch will follow the data input, non-addressed latches will retain their pre • Combined demultiplexer and 8-bit latch\n• Serial-to-parallel capability\n• Output from each storage bit available\n• Random (addressable) data entry\n• Easily expandable\n• Common reset input\n• Useful as a 3-to-8 active HIGH decoder\n• Complies with JEDEC standard no. 7A\n• Input levels:• For 74H;

Nexperia

安世

8-bit addressable latch

The 74HC259-Q100; 74HCT259-Q100 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A.\n The 74HC259-Q100; 74HCT259-Q100 are high-speed 8-bit addressable latches designed for general-purpose stor • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Combined demultiplexer and 8-bit latch\n• Serial-to-parallel capability\n• Output from each storage bit available\n• Random (addressable) data entry\n• Easily exp;

Nexperia

安世

Package：16-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 锁存器 描述：IC 8BIT ADDRESSABL LATCH 16TSSOP

Nexperia USA Inc.

Package：16-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 锁存器 描述：IC 8BIT ADDRESSABL LATCH 16TSSOP

Nexperia USA Inc.