3-to-8 line decoder/demultiplexer

GENERAL DESCRIPTION The 74HC/HCT238 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Demultiplexing capability • Multiple input enable for easy expansion • Ideal for mem

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PHI

PHI

3-to-8 line decoder/demultiplexer

General description 74HC238 and 74HCT238 are high-speed Si-gate CMOS devices and are pin compatible with Low-Power Schottky TTL (LSTTL). The 74HC238/74HCT238 decoders accept three binary weighted address inputs (A0, A1, A2) and when enabled, provide 8 mutually exclusive active HIGH outputs (

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恩XP

3-to-8 line decoder/demultiplexer

1. General description The 74HC238; 74HCT238 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1 and E2 and E3). Every output will be LOW unless E1 and E2 are LOW and E3 is HIGH. This multiple e

文件：267.32 Kbytes 页数：15 Pages

NEXPERIA

安世

3-to-8-line Decoder/Demultiplexer

Description\nThe HD74HC238 has 3 binary select inputs (A, B and C). If the device is enabled these inputs determine which one of the eight normally high outputs will go low. Two active low and one active high enables (G1, G2A and G2B) are provided to ease the cascading of decoders. • High Speed Operation: tpd (Data to Y) = 15 ns typ (CL = 50 pF)\n• High Output Current: Fanout of 10 LSTTL Loads\n• Wide Operating Voltage: VCC = 2 to 6 V\n• Low Input Current: 1 µA max\n• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C);

HITACHI

日立

74系列 逻辑芯片

HGSEMI

华冠

3-to-8 line decoder/demultiplexer

1. General description The 74HC238; 74HCT238 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1 and E2 and E3). Every output will be LOW unless E1 and E2 are LOW and E3 is HIGH. This multiple e

文件：267.32 Kbytes 页数：15 Pages

NEXPERIA

安世

3-to-8 line decoder/demultiplexer

General description 74HC238 and 74HCT238 are high-speed Si-gate CMOS devices and are pin compatible with Low-Power Schottky TTL (LSTTL). The 74HC238/74HCT238 decoders accept three binary weighted address inputs (A0, A1, A2) and when enabled, provide 8 mutually exclusive active HIGH outputs (

文件：120.28 Kbytes 页数：18 Pages

恩XP

3-to-8 line decoder/demultiplexer

1. General description The 74HC238-Q100; 74HCT238-Q100 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1 and E2 and E3). Every output will be LOW unless E1 and E2 are LOW and E3 is HIGH. This

文件：255.08 Kbytes 页数：15 Pages

NEXPERIA

安世

3-to-8 line decoder/demultiplexer

1. General description The 74HC238; 74HCT238 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1 and E2 and E3). Every output will be LOW unless E1 and E2 are LOW and E3 is HIGH. This multiple e

文件：267.32 Kbytes 页数：15 Pages

NEXPERIA

安世

3-to-8 line decoder/demultiplexer

General description 74HC238 and 74HCT238 are high-speed Si-gate CMOS devices and are pin compatible with Low-Power Schottky TTL (LSTTL). The 74HC238/74HCT238 decoders accept three binary weighted address inputs (A0, A1, A2) and when enabled, provide 8 mutually exclusive active HIGH outputs (

文件：120.28 Kbytes 页数：18 Pages

恩XP