3-to-8 line decoder/demultiplexer with address latches

GENERAL DESCRIPTION The 74HC/HCT237 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Combines 3-to-8 decoder with 3-bit latch • Multiple input enable for easy expansion or i

文件：68.32 Kbytes 页数：9 Pages

PHI

飞利浦

3-to-8 line decoder, demultiplexer with address latches

GENERAL DESCRIPTION The 74HC/HCT237 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Combines 3-to-8 decoder with 3-bit latch • Multiple input enable for easy expansion or i

文件：104.03 Kbytes 页数：19 Pages

PHI

飞利浦

3-to-8 line decoder, demultiplexer with address latches

1. General description The 74HC237 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An). The 74HC237 essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When the latch is enabled (LE = LOW), the 74HC237 acts as a 3-to-8 active LOW decode

文件：276.25 Kbytes 页数：16 Pages

NEXPERIA

安世

3-to-8 line decoder, demultiplexer with address latches

General description The 74HC237 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC237 is specified in compliance with JEDEC standard no. 7A. The 74HC237 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An).

文件：165.85 Kbytes 页数：19 Pages

SOLIDSTATE

3-to-8 line decoder, demultiplexer with address latches

文件：150.44 Kbytes 页数：17 Pages

恩XP

3-to-8 line decoder, demultiplexer with address latches

文件：150.44 Kbytes 页数：17 Pages

恩XP

丝印：74HC237D；Package：SOIC16；CMOS Digital Integrated Circuits Silicon Monolithic

Functional Description • 3-to-8 Line Decoder/Latch General The 74HC237D is a high speed CMOS 3-to-8 DECODER ADDRESS LATCH fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. It is c

文件：228.3 Kbytes 页数：10 Pages

TOSHIBA

东芝

3-to-8 line decoder, demultiplexer with address latches

GENERAL DESCRIPTION The 74HC/HCT237 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Combines 3-to-8 decoder with 3-bit latch • Multiple input enable for easy expansion or i

文件：104.03 Kbytes 页数：19 Pages

PHI

飞利浦

3-to-8 line decoder/demultiplexer with address latches

GENERAL DESCRIPTION The 74HC/HCT237 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Combines 3-to-8 decoder with 3-bit latch • Multiple input enable for easy expansion or i

文件：68.32 Kbytes 页数：9 Pages

PHI

飞利浦

3-to-8 line decoder, demultiplexer with address latches

1. General description The 74HC237 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An). The 74HC237 essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When the latch is enabled (LE = LOW), the 74HC237 acts as a 3-to-8 active LOW decode

文件：276.25 Kbytes 页数：16 Pages

NEXPERIA

安世