74HC173DB - Quad D-type flip-flop; positive-edge trigger; 3-state

Quad D-type flip-flop; positive-edge trigger; 3-state - The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will ·Complies with JEDEC standard no. 7A\n·Input levels:·For 74HC173: CMOS level\n·For 74HCT173: TTL level;

Nexperia

安世

Package：16-SSOP（0.209"，5.30mm 宽）；包装：管件 功能：主复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE SNGL 4BIT 16SSOP

Nexperia USA Inc.

Package：16-SSOP（0.209"，5.30mm 宽）；包装：管件 功能：主复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE SNGL 4BIT 16SSOP

Nexperia USA Inc.

Quad D-type flip-flop; positive-edge trigger; 3-state

GENERAL DESCRIPTION The 74HC/HCT173 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT173 are 4-bit parallel load registers with clock enable control, 3-state buffered outputs (

文件：69.04 Kbytes 页数：10 Pages

PHI

飞利浦

Quad D-type flip-flop; positive-edge trigger; 3-state

1. General description The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their co

文件：275.22 Kbytes 页数：17 Pages

NEXPERIA

安世

High Speed CMOS Logic Quad D-Type Flip-Flop, Three-State

文件：57.51 Kbytes 页数：10 Pages

TI

德州仪器