Quad D-type flip-flop; positive-edge trigger; 3-state

1. General description The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their co

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Quad D-type flip-flop; positive-edge trigger; 3-state

The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their corresponding Dn inputs that m • Complies with JEDEC standard no. 7A\n• Input levels:• For 74HC173: CMOS level\n• For 74HCT173: TTL level\n\n• Gated input enable for hold (do nothing) mode\n• Gated output enable control mode\n• Edge-triggered D-type register\n• Asynchronous master reset\n• ESD protection:• HBM JESD22-A114F exceed;

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Package：16-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR） 功能：主复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE SNGL 4BIT 16TSSOP

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

Package：16-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR） 功能：主复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE SNGL 4BIT 16TSSOP

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司