74HC173D

Quad D-type flip-flop; positive-edge trigger; 3-state

1.Generaldescription The74HC173;74HCT173isaquadpositive-edgetriggeredD-typeflip-flop.Thedevicefeatures clock(CP),masterreset(MR),twoinputenable(E1,E2)andtwooutputenable(OE1,OE2)inputs. WhentheinputenablesareLOW,theoutputsQnwillassumethestateoftheirco

74HC173D

Quad D-type flip-flop; positive-edge trigger; 3-state

GENERALDESCRIPTION The74HC/HCT173arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. The74HC/HCT173are4-bitparallelloadregisterswithclockenablecontrol,3-statebufferedoutputs(

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74HC173D

Quad D-type flip-flop; positive-edge trigger; 3-state; • Complies with JEDEC standard no. 7A\n• Input levels:• For 74HC173: CMOS level\n• For 74HCT173: TTL level\n\n• Gated input enable for hold (do nothing) mode\n• Gated output enable control mode\n• Edge-triggered D-type register\n• Asynchronous master reset\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n• Specified from —40 °C to +85 °C and —40 °C to +125 °C\n;

The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on either input enable will cause the device to go into a hold mode, outputs hold their previous state independently of clock and data inputs. A HIGH on MR forces the outputs LOW independently of clock and data inputs. A HIGH on either output enable pin causes the outputs to assume a high-impedance OFF-state. Operation of the output enable inputs does not affect the state of the flip-flops. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.\n

74HC173DB

74HC173DB - Quad D-type flip-flop; positive-edge trigger; 3-state; ·Complies with JEDEC standard no. 7A\n·Input levels:·For 74HC173: CMOS level\n·For 74HCT173: TTL level\n;

Quad D-type flip-flop; positive-edge trigger; 3-state - The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on either input enable will cause the device to go into a hold mode, outputs hold their previous state independently of clock and data inputs. A HIGH on MR forces the outputs LOW independently of clock and data inputs. A HIGH on either output enable pin causes the outputs to assume a high-impedance OFF-state. Operation of the output enable inputs does not affect the state of the flip-flops. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

74HC173D-Q100

Quad D-type flip-flop; positive-edge trigger; 3-state;

The 74HC173-Q100; 74HCT173-Q100 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on either input enable will cause the device to go into a hold mode, outputs hold their previous state independently of clock and data inputs. A HIGH on MR forces the outputs LOW independently of clock and data inputs. A HIGH on either output enable pin causes the outputs to assume a high-impedance OFF-state. Operation of the output enable inputs does not affect the state of the flip-flops. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.\n This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.\n

74HC173D,653

Package：16-SOIC（0.154"，3.90mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 功能：主复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE SNGL 4BIT 16SO

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74HC173DB,112

Package：16-SSOP（0.209"，5.30mm 宽）；包装：管件 功能：主复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE SNGL 4BIT 16SSOP

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74HC173DB,118

Package：16-SSOP（0.209"，5.30mm 宽）；包装：管件 功能：主复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE SNGL 4BIT 16SSOP

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