Quad 3?뭆tate Noninverting Buffers

The 74HC125 is identical in pinout to the LS125. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC125 noninverting buffer is designed to be used with 3−state memory address drivers, clock drivers, and other bus−orien

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ONSEMI

安森美半导体

Quad 3?뭆tate Noninverting Buffers

Quad 3−State Noninverting Buffers High−Performance Silicon−Gate CMOS The MC74HC125A and MC74HC126A are identical in pinout to the LS125 and LS126. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC125A and HC126A n

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ONSEMI

安森美半导体

Quad buffer/line driver; 3-state

GENERAL DESCRIPTION The 74HC/HCT125 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: bus driver • ICC category: MSI

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PHI

飞利浦

QUADRUPLE 3-STATE BUFFERS OE LOW

Description The 74HC125 provides provides four independent buffer gates with 3-state outputs. Each buffer has a separate enable pin that if driven with a high logic level places the corresponding output in the high impedance state. The device is designed for operation with a power supply range of

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DIODES

美台半导体

High Speed CMOS Logic

Features Output Drive Capability: 15 LSTTL Loads Low Input Current: 1μA Outputs directly interface CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V Function compatible with 74LS125 High Noise Immunity CMOS process.

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SS

Quad buffer/line driver; 3-state

1. General description The 74HC125; 74HCT125 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A HIGH on nOE causes the outputs to assume a high impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to

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NEXPERIA

安世

QUAD BUS BUFFERS (3-STATE)

DESCRIPTION The M54/74HC125/126 are high speed CMOS QUAD BUS BUFFER (3-STATE) FABRICATED IN SILICON GATE C2MOS technology. They have the same high speed performance of LSTTL combined with true CMOS low power consumption. These devices require the same 3-STATE control input G to be taken hig

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SOLIDSTATE

丝印：74HC125D；Package：SOIC14；CMOS Digital Integrated Circuits Silicon Monolithic

Functional Description • Quad Bus Buffer, Non-Inverted 3-State Outputs 74HC125D: Quad Bus Buffer 74HC126D: Quad Bus Buffer General The 74HC125D,74HC126D are high speed CMOS QUAD BUS BUFFERs fabricated with silicon gate C2MOS technology. They achieve the high speed operation similar to equiv

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TOSHIBA

东芝

Standard-logic

The 74HC125 provides provides four independent buffer gates with\n3-state outputs. Each buffer has a separate enable pin that if driven\nwith a high logic level places the corresponding output in the high\nimpedance state. The device is designed for operation with a power\nsupply range of 2.0V to 6.

Diodes

美台半导体

QUAD BUS BUFFERS (3-STATE)

ST

意法半导体