Dual JK flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)

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PHI

飞利浦

Dual JK flip-flop with set and reset; positive-edge-trigger

1. General description The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of

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NEXPERIA

安世

Dual JK flip-flop with set and reset; positive-edge-trigger

The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and • J and K inputs for easy D-type flip-flop\n• Toggle flip-flop or \"do nothing\" mode\n• Wide supply voltage range:• For 74HC109: from 2.0 V to 6.0 V\n• For 74HCT109: from 4.5 V to 5.5 V\n\n• CMOS low power dissipation\n• High noise immunity\n• Input levels:• For 74HC109: CMOS level\n• For 74HCT109:;

Nexperia

安世

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

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TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

文件：279.59 Kbytes 页数：12 Pages

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

文件：347.95 Kbytes 页数：16 Pages

TI

德州仪器