丝印：74F08；Package：SOP；QUADRUPLE 2-INPUT POSITIVE-AND GATE

Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs description The SN74F08 contains four independent 2-input AND gates. It performs the Boolean functions Y = A • B or Y = A + B in positive logic. The SN74F08 is characterized for operation from 0°C to

文件：630.48 Kbytes 页数：16 Pages

TI

德州仪器

丝印：74F08；Package：SOP；QUADRUPLE 2-INPUT POSITIVE-AND GATE

Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs description The SN74F08 contains four independent 2-input AND gates. It performs the Boolean functions Y = A • B or Y = A + B in positive logic. The SN74F08 is characterized for operation from 0°C to

文件：630.48 Kbytes 页数：16 Pages

TI

德州仪器

丝印：74F112；Package：SOP；DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET

Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs description The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of t

文件：566.64 Kbytes 页数：16 Pages

TI

德州仪器

丝印：74F112；Package：SOP；DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET

Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs description The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of t

文件：566.64 Kbytes 页数：16 Pages

TI

德州仪器

丝印：74F125；Package：SOP；QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

3-State Outputs Drive Bus Lines or Buffer Memory Address Registers description/ordering information The SN74F125 features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.

文件：523.46 Kbytes 页数：15 Pages

TI

德州仪器

丝印：74F125；Package：SOP；QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

3-State Outputs Drive Bus Lines or Buffer Memory Address Registers description/ordering information The SN74F125 features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.

文件：523.46 Kbytes 页数：15 Pages

TI

德州仪器

丝印：74F161A；Package：SOP；SYNCHRONOUS 4-BIT BINARY COUNTER

Internal Look-Ahead Circuitry for Fast Counting Carry Output for N-Bit Cascading Fully Synchronous Operation for Counting description This synchronous, presettable, 4-bit binary counter has internal carry look-ahead circuitry for use in high-speed counting designs. Synchronous operation

文件：625.09 Kbytes 页数：20 Pages

TI

德州仪器

丝印：74F161A；Package：SOP；SYNCHRONOUS 4-BIT BINARY COUNTER

Internal Look-Ahead Circuitry for Fast Counting Carry Output for N-Bit Cascading Fully Synchronous Operation for Counting description This synchronous, presettable, 4-bit binary counter has internal carry look-ahead circuitry for use in high-speed counting designs. Synchronous operation

文件：625.09 Kbytes 页数：20 Pages

TI

德州仪器

丝印：74F175；Package：SOP；QUADRUPLE D-TYPE FLIP-FLOP WITH CLEAR

Contains Four Flip-Flops With Double-Rail Outputs Buffered Clock and Direct Clear Inputs Applications Include: – Buffer/Storage Registers – Shift Registers – Pattern Generators description This positive-edge-triggered flip-flop utilizes TTL circuitry to implement D-type flip-flop logic

文件：572.1 Kbytes 页数：16 Pages

TI

德州仪器

丝印：74F175；Package：SOP；QUADRUPLE D-TYPE FLIP-FLOP WITH CLEAR

Contains Four Flip-Flops With Double-Rail Outputs Buffered Clock and Direct Clear Inputs Applications Include: – Buffer/Storage Registers – Shift Registers – Pattern Generators description This positive-edge-triggered flip-flop utilizes TTL circuitry to implement D-type flip-flop logic

文件：572.1 Kbytes 页数：16 Pages

TI

德州仪器