Low-power D-type flip-flop with reset; positive-edge trigger

文件：110.86 Kbytes 页数：20 Pages

恩XP

Low-power D-type flip-flop with reset; positive-edge trigger

文件：92.11 Kbytes 页数：26 Pages

PHI

PHI

Low-power D-type flip-flop with reset; positive-edge trigger

文件：110.86 Kbytes 页数：20 Pages

恩XP

丝印：aT；Package：SC-88；Low-power D-type flip-flop with reset; positive-edge trigger

文件：219.07 Kbytes 页数：17 Pages

NEXPERIA

安世

Low-power D-type flip-flop with reset; positive-edge trigger

文件：219.07 Kbytes 页数：17 Pages

NEXPERIA

安世

Low-power D-type flip-flop with reset; positive-edge trigger

The 74AUP1G175 provides a low-power, low-voltage positive-edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the clock input. Information on t • Wide supply voltage range from 0.8 V to 3.6 V\n• High noise immunity\n• Complies with JEDEC standards:• JESD8-12 (0.8 V to 1.3 V)\n• JESD8-11 (0.9 V to 1.65 V)\n• JESD8-7 (1.2 V to 1.95 V)\n• JESD8-5 (1.8 V to 2.7 V)\n• JESD8-B (2.7 V to 3.6 V)\n\n• ESD protection:• HBM JESD22-A114F Class 3A excee;

Nexperia

安世

Low-power D-type flip-flop with reset; positive-edge trigger

The 74AUP1G175 provides a low-power, low-voltage positive-edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the clock input. Information on t • Wide supply voltage range from 0.8 V to 3.6 V\n• High noise immunity\n• Complies with JEDEC standards:• JESD8-12 (0.8 V to 1.3 V)\n• JESD8-11 (0.9 V to 1.65 V)\n• JESD8-7 (1.2 V to 1.95 V)\n• JESD8-5 (1.8 V to 2.7 V)\n• JESD8-B (2.7 V to 3.6 V)\n\n• ESD protection:• HBM JESD22-A114F Class 3A excee;

Nexperia

安世

Low-power D-type flip-flop with reset; positive-edge trigger

The 74AUP1G175 provides a low-power, low-voltage positive-edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the clock input. Information on t • Wide supply voltage range from 0.8 V to 3.6 V\n• High noise immunity\n• Complies with JEDEC standards:• JESD8-12 (0.8 V to 1.3 V)\n• JESD8-11 (0.9 V to 1.65 V)\n• JESD8-7 (1.2 V to 1.95 V)\n• JESD8-5 (1.8 V to 2.7 V)\n• JESD8-B (2.7 V to 3.6 V)\n\n• ESD protection:• HBM JESD22-A114F Class 3A excee;

Nexperia

安世

Package：6-XFDFN；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 功能：复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE SNGL 1BIT 6XSON

Nexperia USA Inc.

Package：6-XFDFN；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 功能：复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE SNGL 1BIT 6XSON

Nexperia USA Inc.