Low-power 2-input AND gate

1. General description The 74AUP1G08 is a single 2-input AND gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device

文件：273.54 Kbytes 页数：18 Pages

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安世

Low-power 2-input AND gate

文件：84.23 Kbytes 页数：17 Pages

PHI

PHI

SINGLE 2 INPUT POSITIVE AND GATE

文件：187.65 Kbytes 页数：11 Pages

DIODES

美台半导体

Low Power Single 2-Input Positive-AND Gate

The 74AUP1G08 is a low power single 2-input positive-AND gate which can accept supply voltage range from 0.8V to 3.6V. All of the inputs support Schmitt-trigger action. The device features low static power dissipation over the wide supply voltage range and implements Boolean function Y = A ∙ B or Y ● Wide Supply Voltage Range: 0.8V to 3.6V● Inputs Accept Voltages Higher than the Supply Voltage● +4mA/-4mA Output Current● Low Static Power Dissipation: ICC = 0.1μA (TYP)● Low Dynamic-Power Dissipation: CPD = 6.5pF (TYP) at VCC = 3.3V● All Inputs with Schmitt-Trigger● Support Partial Power-Down Mod;

SGMICRO

圣邦股份

Single-gate

The Advanced Ultra Low Power (AUP) CMOS logic family is designed\nfor low power and extended battery life in portable applications.\n\nThe 74AUP1G08 is a single 2-input positive AND gate with a\nstandard push-pull output designed for operation over a power supply\nrange of 0.8V to 3.6V. The device i •Advanced Ultra Low Power (AUP) CMOS•Supply Voltage Range from 0.8V to 3.6V•±4mA Output Drive at 3.0V•Low Static power consumption;

Diodes

美台半导体

Low-power 3-input AND-OR gate

1. General description The 74AUP1G0832 is a single 3-input AND-OR gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This de

文件：259.62 Kbytes 页数：16 Pages

NEXPERIA

安世

丝印：AY；Package：XSON6；Low-power 3-input AND-OR gate

1. General description The 74AUP1G0832 is a single 3-input AND-OR gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This de

文件：259.62 Kbytes 页数：16 Pages

NEXPERIA

安世

丝印：AY；Package：XSON6；Low-power 3-input AND-OR gate

1. General description The 74AUP1G0832 is a single 3-input AND-OR gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This de

文件：259.62 Kbytes 页数：16 Pages

NEXPERIA

安世

丝印：AY；Package：XSON6；Low-power 3-input AND-OR gate

1. General description The 74AUP1G0832 is a single 3-input AND-OR gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This de

文件：259.62 Kbytes 页数：16 Pages

NEXPERIA

安世

丝印：AY；Package：TSSOP6；Low-power 3-input AND-OR gate

1. General description The 74AUP1G0832 is a single 3-input AND-OR gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This de

文件：259.62 Kbytes 页数：16 Pages

NEXPERIA

安世