18-bit bus-interface D-type latch 3-State

DESCRIPTION The 74ALVCH16843 has two 9–bit D-type latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. FEATURES • Wide supply voltage range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A. • CMOS low power consumption • Direct

文件：84.39 Kbytes 页数：12 Pages

PHI

PHI

18-bit bus-interface D-type latch; 3-State

1 General description The 74ALVCH16843 has two 9–bit D-type latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. The two sections of each register are controlled independently by the latch enable (nLE), clear (nCLR), preset (nPRE) and output

文件：204.98 Kbytes 页数：16 Pages

NEXPERIA

安世

18-bit bus-interface D-type latch; 3-State

1 General description The 74ALVCH16843 has two 9–bit D-type latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. The two sections of each register are controlled independently by the latch enable (nLE), clear (nCLR), preset (nPRE) and output

文件：204.98 Kbytes 页数：16 Pages

NEXPERIA

安世

18-bit bus-interface D-type latch 3-State

DESCRIPTION The 74ALVCH16843 has two 9–bit D-type latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. FEATURES • Wide supply voltage range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A. • CMOS low power consumption • Direct

文件：84.39 Kbytes 页数：12 Pages

PHI

PHI

18-bit bus-interface D-type latch (3-State)

文件：88.73 Kbytes 页数：12 Pages

PHI

PHI

18-bit bus-interface D-type latch; 3-state

The 74ALVCH16843 has two 9-bit D-type latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. The two sections of each register are controlled independently by the latch enable (nLE) clear (nCLR) preset (nPRE) and output enable (nOE) control gates.\n • Wide supply voltage range of 1.2 V to 3.6 V\n• Complies with JEDEC standard no. 8-1A.\n• CMOS low power consumption\n• Direct interface with TTL levels\n• Current drive ±24 mA at 3.0 V\n• MULTIBYTE™™ flow-through standard pin-out architecture\n• Low inductance multiple VCC and GND pins for minimum;

Nexperia

安世

Package：56-TFSOP（0.240"，6.10mm 宽）；包装：管件 类别：集成电路（IC） 锁存器 描述：IC 18BIT BUS INTRFC D 56TSSOP

Nexperia USA Inc.

Package：56-TFSOP（0.240"，6.10mm 宽）；包装：管件 类别：集成电路（IC） 锁存器 描述：IC BUS-INTERFACE LATCH 56TSSOP

Nexperia USA Inc.

Package：56-TFSOP（0.240"，6.10mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 锁存器 描述：IC INTERFACE 18BIT BUS 56TSSOP

Nexperia USA Inc.