18-bit bus-interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ALVCH16823 is a 18-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. FEATURES • Wide supply voltage range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A. • CMOS low power consumpt

文件：103.3 Kbytes 页数：12 Pages

PHI

PHI

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

1 General description The 74ALVCH16823 is a 18-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. Incorporates bushold data inputs which eliminate the need for external pull-up resistors to hold unused inputs. The

文件：218.45 Kbytes 页数：18 Pages

NEXPERIA

安世

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

1 General description The 74ALVCH16823 is a 18-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. Incorporates bushold data inputs which eliminate the need for external pull-up resistors to hold unused inputs. The

文件：218.45 Kbytes 页数：18 Pages

NEXPERIA

安世

18-bit bus-interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ALVCH16823 is a 18-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. FEATURES • Wide supply voltage range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A. • CMOS low power consumpt

文件：103.3 Kbytes 页数：12 Pages

PHI

PHI

18-bit bus-interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ALVCH16823 is a 18-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. FEATURES • Wide supply voltage range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A. • CMOS low power consumpt

文件：103.3 Kbytes 页数：12 Pages

PHI

PHI

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

The 74ALVCH16823 is a 18-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. Incorporates bushold data inputs which eliminate the need for external pull-up resistors to hold unused inputs. The 74ALVCH16823 consists of tw • Wide supply voltage range from 1.2 V to 3.6 V\n• CMOS low-power consumption\n• Direct interface with TTL levels\n• Current drive ± 24 mA at 3.0 V\n• MULTIBYTE flow-through standard pin-out architecture\n• Low inductance multiple VCC and GND pins for minimum noise and ground bounce\n• Output drive ;

Nexperia

安世

Package：56-TFSOP（0.240"，6.10mm 宽）；包装：管件 功能：主复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE DUAL 9BIT 56TSSOP

Nexperia USA Inc.

Package：56-TFSOP（0.240"，6.10mm 宽）；包装：管件 功能：主复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE DUAL 9BIT 56TSSOP

Nexperia USA Inc.

Package：56-TFSOP（0.240"，6.10mm 宽）；包装：管件 功能：主复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE DUAL 9BIT 56TSSOP

Nexperia USA Inc.