20-bit bus-interface D-type flip-flop; positive-edge trigger 3-State

DESCRIPTION The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-State output buffer. The two sections of each register are controlled independently by the clock (nCP) and Output Enable (nOE) control gates. FEATURES • Wide supply voltage range of

文件：95.31 Kbytes 页数：12 Pages

PHI

PHI

20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state

1 General description The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-state output buffer. The two sections of each register are controlled independently by the clock (nCP) and output enable (nOE) control gates. Each register is fully edge triggered

文件：199.31 Kbytes 页数：15 Pages

NEXPERIA

安世

20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state

1 General description The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-state output buffer. The two sections of each register are controlled independently by the clock (nCP) and output enable (nOE) control gates. Each register is fully edge triggered

文件：199.31 Kbytes 页数：15 Pages

NEXPERIA

安世

20-bit bus-interface D-type flip-flop; positive-edge trigger 3-State

DESCRIPTION The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-State output buffer. The two sections of each register are controlled independently by the clock (nCP) and Output Enable (nOE) control gates. FEATURES • Wide supply voltage range of

文件：95.31 Kbytes 页数：12 Pages

PHI

PHI

20-bit bus-interface D-type flip-flop; positive-edge trigger 3-State

DESCRIPTION The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-State output buffer. The two sections of each register are controlled independently by the clock (nCP) and Output Enable (nOE) control gates. FEATURES • Wide supply voltage range of

文件：95.31 Kbytes 页数：12 Pages

PHI

PHI

3.3-V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

文件：312.07 Kbytes 页数：12 Pages

TI

德州仪器

3.3-V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

文件：312.07 Kbytes 页数：12 Pages

TI

德州仪器

3.3-V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

文件：312.07 Kbytes 页数：12 Pages

TI

德州仪器

3.3-V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

文件：312.07 Kbytes 页数：12 Pages

TI

德州仪器

20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state

The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-state output buffer. The two sections of each register are controlled independently by the clock (nCP) and output enable (nOE) control gates.\n Each register is fully edge triggered. The state of each nDn • Wide supply voltage range from 1.2 V to 3.6 V\n• CMOS low-power consumption\n• Direct interface with TTL levels\n• Current drive ± 24 mA at 3.0 V\n• MULTIBYTE flow-through standard pin-out architecture\n• Low inductance multiple VCC and GND pins for minimum noise and ground bounce\n• Output drive ;

Nexperia

安世