18-bit universal bus transceiver 3-State

DESCRIPTION The 74ALVCH16501 is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. F

文件：86.9 Kbytes 页数：13 Pages

PHI

PHI

18-bit universal bus transceiver; 3-state

General description The 74ALVCH16501 is an 18-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For

文件：377.27 Kbytes 页数：18 Pages

恩XP

18-bit universal bus transceiver; 3-state

1. General description The 74ALVCH16501 is an 18-bit universal transceiver with bus hold inputs and 3-state outputs. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device opera

文件：253.8 Kbytes 页数：15 Pages

NEXPERIA

安世

18-bit universal bus transceiver; 3-state

1. General description The 74ALVCH16501 is an 18-bit universal transceiver with bus hold inputs and 3-state outputs. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device opera

文件：253.8 Kbytes 页数：15 Pages

NEXPERIA

安世

18-bit universal bus transceiver; 3-state

General description The 74ALVCH16501 is an 18-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For

文件：377.27 Kbytes 页数：18 Pages

恩XP

18-bit universal bus transceiver 3-State

DESCRIPTION The 74ALVCH16501 is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. F

文件：86.9 Kbytes 页数：13 Pages

PHI

PHI

丝印：ALVCH16501；Package：TSSOP；18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

FEATURES · Member of the Texas Instruments Widebus™ Family · UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Modes · Operates From 1.65 V to 3.6 V · Max tpd of 3.9 ns at 3.3 V · ±24-mA Output Drive at 3.3 V · Bus Hold on Dat

文件：570.38 Kbytes 页数：16 Pages

TI

德州仪器

18-bit universal bus transceiver; 3-state

General description The 74ALVCH16501 is an 18-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For

文件：377.27 Kbytes 页数：18 Pages

恩XP

18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

FEATURES · Member of the Texas Instruments Widebus™ Family · UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Modes · Operates From 1.65 V to 3.6 V · Max tpd of 3.9 ns at 3.3 V · ±24-mA Output Drive at 3.3 V · Bus Hold on Dat

文件：570.38 Kbytes 页数：16 Pages

TI

德州仪器

18-bit universal bus transceiver; 3-state

文件：230.32 Kbytes 页数：18 Pages

PHI

PHI