General description

The 74ALVCH16501 is an 18-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to HIGH transition of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state.

Features and benefits

■ Wide supply voltage range from 1.2 V to 3.6 V

■ Complies with JEDEC standard JESD8-B

■ CMOS low power consumption

■ Direct interface with TTL levels

■ Current drive ±24 mA at VCC = 3.0 V

■ Universal bus transceiver with D-type latches and D-type flip-flops capable of operating in transparent, latched or clocked mode

■ All inputs have bus hold circuitry

■ Output drive capability 50 Ω transmission lines at 85 °C

■ 3-state non-inverting outputs for bus-oriented applications

74ALVCH16501DGG属于集成电路（IC） > 通用总线功能。恩智浦半导体公司制造生产的74ALVCH16501DGG通用总线功能通用总线功能系列产品是元件级产品，用于处理或操作一系列（通常为 8 个或更多）并行逻辑信号（称为总线）。所执行的功能包括临时存储要发送或接收的数据，执行缓冲以允许输出电流容量有限的器件（例如微处理器）通过远距离互连高速传输数据，以及调换或移动总线内的位顺序等。