18-bit universal bus transceiver 3-State

DESCRIPTION The 74ALVCH16500 is a high-performance CMOS product. This device is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. FEATURES • Complies with JEDEC standard no. 8-1A • CMOS low power consumption • Direct in

文件：88.45 Kbytes 页数：14 Pages

PHI

PHI

18-bit universal bus transceiver; 3-state

1 General description The 74ALVCH16500 is a high-performance CMOS product. This device is an 18-bit universal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latc

文件：210.05 Kbytes 页数：17 Pages

NEXPERIA

安世

18-bit universal bus transceiver; 3-state

1 General description The 74ALVCH16500 is a high-performance CMOS product. This device is an 18-bit universal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latc

文件：210.05 Kbytes 页数：17 Pages

NEXPERIA

安世

18-bit universal bus transceiver 3-State

DESCRIPTION The 74ALVCH16500 is a high-performance CMOS product. This device is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. FEATURES • Complies with JEDEC standard no. 8-1A • CMOS low power consumption • Direct in

文件：88.45 Kbytes 页数：14 Pages

PHI

PHI

18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

文件：355.01 Kbytes 页数：15 Pages

TI

德州仪器

18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

文件：355.01 Kbytes 页数：15 Pages

TI

德州仪器

18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

文件：355.01 Kbytes 页数：15 Pages

TI

德州仪器

18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

文件：355.01 Kbytes 页数：15 Pages

TI

德州仪器

18-bit universal bus transceiver (3-State)

The 74ALVCH16500 is a high-performance CMOS product. This device is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA) latch enable (LEAB and LEBA)and c • Complies with JEDEC standard no. 8-1A\n• CMOS low power consumption\n• Direct interface with TTL levels\n• Current drive ± 24 mA at 3.0 V\n• All inputs have bushold circuitry\n• Output drive capability 50Ω transmission lines @ 85°C\n• MULTIBYTE™™ flow-through standard pin-out architecture\n• Low i;

Nexperia

安世

Package：56-TFSOP（0.240"，6.10mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 通用总线功能 描述：IC UNIV BUS TXRX 18BIT 56TSSOP

TI

德州仪器