Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74ALVC74 is a dual positive-edge triggered, D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on t

文件：103.39 Kbytes 页数：20 Pages

PHI

飞利浦

Dual D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74ALVC74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs that operate independently of th

文件：258.67 Kbytes 页数：16 Pages

NEXPERIA

安世

Dual D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74ALVC74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs that operate independently of th

文件：258.67 Kbytes 页数：16 Pages

NEXPERIA

安世

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74ALVC74 is a dual positive-edge triggered, D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on t

文件：103.39 Kbytes 页数：20 Pages

PHI

飞利浦

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74ALVC74 is a dual positive-edge triggered, D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on t

文件：103.39 Kbytes 页数：20 Pages

PHI

飞利浦

Dual D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74ALVC74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs that operate independently of th

文件：258.67 Kbytes 页数：16 Pages

NEXPERIA

安世

Dual D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74ALVC74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs that operate independently of th

文件：258.67 Kbytes 页数：16 Pages

NEXPERIA

安世

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74ALVC74 is a dual positive-edge triggered, D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on t

文件：103.39 Kbytes 页数：20 Pages

PHI

飞利浦

Dual D-type flip-flop with set and reset; positive-edge trigger

The 74ALVC74 is a dual positive-edge triggered, D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs.\n The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data inp • Wide supply voltage range from 1.65 V to 3.6 V\n• Complies with JEDEC standard:• JESD8-7 (1.65 V to 1.95 V)\n• JESD8-5 (2.3 V to 2.7 V)\n• JESD8B/JESD36 (2.7 V to 3.6 V)\n\n• 3.6 V tolerant inputs/outputs\n• CMOS low power consumption\n• Direct interface with TTL levels (2.7 V to 3.6 V)\n• Power-d;

Nexperia

安世

Dual D-type flip-flop with set and reset; positive-edge trigger

The 74ALVC74 is a dual positive-edge triggered, D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs.\n The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data inp • Wide supply voltage range from 1.65 V to 3.6 V\n• Complies with JEDEC standard:• JESD8-7 (1.65 V to 1.95 V)\n• JESD8-5 (2.3 V to 2.7 V)\n• JESD8B/JESD36 (2.7 V to 3.6 V)\n\n• 3.6 V tolerant inputs/outputs\n• CMOS low power consumption\n• Direct interface with TTL levels (2.7 V to 3.6 V)\n• Power-d;

Nexperia

安世