Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74ALVC74 is a dual positive-edge triggered, D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on t

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PHI

PHI

Dual D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74ALVC74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs that operate independently of th

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NEXPERIA

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Dual D-type flip-flop with set and reset; positive-edge trigger

The 74ALVC74 is a dual positive-edge triggered, D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs.\n The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data inp • Wide supply voltage range from 1.65 V to 3.6 V\n• Complies with JEDEC standard:• JESD8-7 (1.65 V to 1.95 V)\n• JESD8-5 (2.3 V to 2.7 V)\n• JESD8B/JESD36 (2.7 V to 3.6 V)\n\n• 3.6 V tolerant inputs/outputs\n• CMOS low power consumption\n• Direct interface with TTL levels (2.7 V to 3.6 V)\n• Power-d;

Nexperia

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Dual D-type flip-flop with set and reset; positive-edge trigger

The 74ALVC74-Q100 is a dual positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Wide supply voltage range from 1.65 V to 3.6 V\n• CMOS low power dissipation\n• Overvoltage tolerant inputs to 3.6 V\n• Direct interface with TTL levels\n• IOFF c;

Nexperia

安世

Package：14-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 功能：设置（预设）和复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE DUAL 1BIT 14TSSOP

Nexperia USA Inc.

Package：14-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 功能：设置（预设）和复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE DUAL 1BIT 14TSSOP

Nexperia USA Inc.