20-bit registered driver with inverted register enable and 30ohm termination resistors 3-State

DESCRIPTION The 74ALVC162836A is an 20-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). When LE is HIGH, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH tr

文件：121.92 Kbytes 页数：12 Pages

PHI

PHI

20-bit registered driver with inverted register enable and 30 Ω termination resistors; 3-state

1 General description The 74ALVC162836A is a 20-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). When LE is HIGH, the An to Yn data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on the L

文件：204.75 Kbytes 页数：15 Pages

NEXPERIA

安世

20-bit registered driver with inverted register enable and 30ohm termination resistors 3-State

文件：100.32 Kbytes 页数：12 Pages

PHI

PHI

20-bit registered driver with inverted register enable and 30ohm termination resistors 3-State

DESCRIPTION The 74ALVC162836A is an 20-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). When LE is HIGH, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH tr

文件：121.92 Kbytes 页数：12 Pages

PHI

PHI

20-bit registered driver with inverted register enable and 30 Ω termination resistors; 3-state

1 General description The 74ALVC162836A is a 20-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). When LE is HIGH, the An to Yn data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on the L

文件：204.75 Kbytes 页数：15 Pages

NEXPERIA

安世

20-bit registered driver with inverted register enable and 30ohm termination resistors 3-State

文件：100.32 Kbytes 页数：12 Pages

PHI

PHI

20-bit registered driver with inverted register enable and 30ohm termination resistors 3-State

文件：100.32 Kbytes 页数：12 Pages

PHI

PHI

20-bit registered driver with inverted register enable and 30 Ω termination resistors (3-state)

The 74ALVC162836A is an 20-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP).\n When LE is HIGH, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH transient of • Wide supply voltage range of 1.2 V to 3.6 V\n• Complies with JEDEC standard no. 8-1A\n• CMOS low power consumption\n• Direct interface with TTL levels\n• Current drive ±12 mA at 3.0 V\n• MULTIBYTETM flow-through standard pin-out architecture\n• Low inductance multiple VCC and GND pins for minimum ;

Nexperia

安世

Package：56-TFSOP（0.240"，6.10mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 通用总线功能 描述：IC UNIV BUS DVR 20BIT 56TSSOP

Nexperia USA Inc.

Package：56-TFSOP（0.240"，6.10mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 通用总线功能 描述：IC UNIV BUS DVR 20BIT 56TSSOP

Nexperia USA Inc.