74ALVC162836ADGG数据手册集成电路（IC）的通用总线功能规格书PDF

描述 Description

The 74ALVC162836A is an 20-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP).
When LE is HIGH, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP the A-data is stored in the latch/flip-flop.
The 74ALVC162836A is designed with 30 Ω series resistors in both HIGH or LOW output stages.
When OE is LOW the outputs are active. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latch/flip-flop.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

特性 Features

• Wide supply voltage range of 1.2 V to 3.6 V
• Complies with JEDEC standard no. 8-1A
• CMOS low power consumption
• Direct interface with TTL levels
• Current drive ±12 mA at 3.0 V
• MULTIBYTETM flow-through standard pin-out architecture
• Low inductance multiple VCC and GND pins for minimum noise and ground bounce
• Output drive capability 50 Ω transmission lines @ 85 °C
• Integrated 30 Ω termination resistors
• Diode clamps to VCC and GND on all inputs
• Input diodes to accommodate strong drivers