Octal D-type transparent latch; 3-state

1. General description The 74ALVC573 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A latch enable (LE) input and an outputs enable (OE) input are common to all latches. When pin LE is HIGH, data at t

文件：268.43 Kbytes 页数：16 Pages

NEXPERIA

安世

Octal D-type transparent latch; 3-state

1. General description The 74ALVC573 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A latch enable (LE) input and an outputs enable (OE) input are common to all latches. When pin LE is HIGH, data at t

文件：268.43 Kbytes 页数：16 Pages

NEXPERIA

安世

Octal D-type transparent latch; 3-state

1. General description The 74ALVC573 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A latch enable (LE) input and an outputs enable (OE) input are common to all latches. When pin LE is HIGH, data at t

文件：268.43 Kbytes 页数：16 Pages

NEXPERIA

安世

Octal D-type transparent latch; 3-state

1. General description The 74ALVC573 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A latch enable (LE) input and an outputs enable (OE) input are common to all latches. When pin LE is HIGH, data at t

文件：268.43 Kbytes 页数：16 Pages

NEXPERIA

安世

Octal D-type flip-flop; positive edge-trigger; 3-state

1. General description The 74ALVC574 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. A clock input (CP) and an outputs enable input (OE) are common to all flip-flops. The eight flip-flops will store the state o

文件：262.9 Kbytes 页数：15 Pages

NEXPERIA

安世

Octal D-type flip-flop; positive edge-trigger; 3-state

1. General description The 74ALVC574 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. A clock input (CP) and an outputs enable input (OE) are common to all flip-flops. The eight flip-flops will store the state o

文件：262.9 Kbytes 页数：15 Pages

NEXPERIA

安世

Octal D-type flip-flop; positive edge-trigger; 3-state

1. General description The 74ALVC574 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. A clock input (CP) and an outputs enable input (OE) are common to all flip-flops. The eight flip-flops will store the state o

文件：262.9 Kbytes 页数：15 Pages

NEXPERIA

安世

Octal D-type flip-flop; positive edge-trigger; 3-state

1. General description The 74ALVC574 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. A clock input (CP) and an outputs enable input (OE) are common to all flip-flops. The eight flip-flops will store the state o

文件：262.9 Kbytes 页数：15 Pages

NEXPERIA

安世

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74ALVC74 is a dual positive-edge triggered, D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on t

文件：103.39 Kbytes 页数：20 Pages

PHI

PHI

Dual D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74ALVC74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs that operate independently of th

文件：258.67 Kbytes 页数：16 Pages

NEXPERIA

安世