Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74ALVC74 is a dual positive-edge triggered, D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on t

文件：103.39 Kbytes 页数：20 Pages

PHI

PHI

Dual D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74ALVC74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs that operate independently of th

文件：258.67 Kbytes 页数：16 Pages

NEXPERIA

安世

Dual D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74ALVC74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs that operate independently of th

文件：258.67 Kbytes 页数：16 Pages

NEXPERIA

安世

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74ALVC74 is a dual positive-edge triggered, D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on t

文件：103.39 Kbytes 页数：20 Pages

PHI

PHI

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74ALVC74 is a dual positive-edge triggered, D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on t

文件：103.39 Kbytes 页数：20 Pages

PHI

PHI

Dual D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74ALVC74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs that operate independently of th

文件：258.67 Kbytes 页数：16 Pages

NEXPERIA

安世

Low Voltage Quad 2-Input Exclusive-OR Gate with 3.6V Tolerant Inputs and Outputs

General Description The ALVC86 contains four 2-input exclusive OR gates. This product is designed for low voltage (1.65V to 3.6V) VCC applications with I/O compatibility up to 3.6V. The 74ALVC86 is fabricated with an advanced CMOS technology to achieve high-speed operation while maintaining low

文件：71.88 Kbytes 页数：5 Pages

FAIRCHILD

仙童半导体

Low Voltage Quad 2-Input Exclusive-OR Gate with 3.6V Tolerant Inputs and Outputs

General Description The ALVC86 contains four 2-input exclusive OR gates. This product is designed for low voltage (1.65V to 3.6V) VCC applications with I/O compatibility up to 3.6V. The 74ALVC86 is fabricated with an advanced CMOS technology to achieve high-speed operation while maintaining low

文件：71.88 Kbytes 页数：5 Pages

FAIRCHILD

仙童半导体

Low Voltage Quad 2-Input Exclusive-OR Gate with 3.6V Tolerant Inputs and Outputs

General Description The ALVC86 contains four 2-input exclusive OR gates. This product is designed for low voltage (1.65V to 3.6V) VCC applications with I/O compatibility up to 3.6V. The 74ALVC86 is fabricated with an advanced CMOS technology to achieve high-speed operation while maintaining low

文件：71.88 Kbytes 页数：5 Pages

FAIRCHILD

仙童半导体

Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Outputs and 26??Series Resistors in Outputs

General Description The 74ALVCF162835 low voltage 18-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes.g The 74ALVCF162835 is designed with 26Ω series resistors in the outputs. This design reduces noise in applicati

文件：106.45 Kbytes 页数：7 Pages

FAIRCHILD

仙童半导体