Quad 2-input OR gate

General description The 74ALVC32 is a quad 2-input OR gate. Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times. Features ■ Wide supply voltage range from 1.65 V to 3.6 V ■ 3.6 V tolerant inputs/outputs ■ CMOS low power consumption ■ Direct interface w

文件：88.31 Kbytes 页数：13 Pages

恩XP

Low Voltage Quad 2-Input OR Gate with 3.6V Tolerant Inputs and Outputs

General Description The ALVC32 contains four 2-input OR gates. This product is designed for low voltage (1.65V to 3.6V) VCC applications with I/O compatibility up to 3.6V. The ALVC32 is fabricated with an advanced CMOS technology to achieve high-speed operation while maintaining low CMOS power d

文件：71.25 Kbytes 页数：5 Pages

FAIRCHILD

仙童半导体

Low Voltage Quad 2-Input OR Gate with 3.6V Tolerant Inputs and Outputs

General Description The ALVC32 contains four 2-input OR gates. This product is designed for low voltage (1.65V to 3.6V) VCC applications with I/O compatibility up to 3.6V. The ALVC32 is fabricated with an advanced CMOS technology to achieve high-speed operation while maintaining low CMOS power d

文件：71.25 Kbytes 页数：5 Pages

FAIRCHILD

仙童半导体

Quad 2-input OR gate

General description The 74ALVC32 is a quad 2-input OR gate. Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times. Features ■ Wide supply voltage range from 1.65 V to 3.6 V ■ 3.6 V tolerant inputs/outputs ■ CMOS low power consumption ■ Direct interface w

文件：88.31 Kbytes 页数：13 Pages

恩XP

Quad 2-input OR gate

1. General description The 74ALVC32 is a quad 2-input OR gate. Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times. 2. Features and benefits • Wide supply voltage range from 1.65 V to 3.6 V • 3.6 V tolerant inputs/outputs • CMOS low power consumption •

文件：232.28 Kbytes 页数：12 Pages

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Octal D-type transparent latch; 3-state

1. General description The 74ALVC373 is an octal D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change e

文件：267.03 Kbytes 页数：15 Pages

NEXPERIA

安世

Octal D-type transparent latch; 3-state

1. General description The 74ALVC373 is an octal D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change e

文件：267.03 Kbytes 页数：15 Pages

NEXPERIA

安世

Octal D-type transparent latch; 3-state

1. General description The 74ALVC373 is an octal D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change e

文件：267.03 Kbytes 页数：15 Pages

NEXPERIA

安世

Octal D-type transparent latch; 3-state

1. General description The 74ALVC373 is an octal D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change e

文件：267.03 Kbytes 页数：15 Pages

NEXPERIA

安世

Octal D-type flip-flop; positive-edge trigger; 3-state

1. General description The 74ALVC374 is an octal positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the

文件：259.6 Kbytes 页数：15 Pages

NEXPERIA

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