Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74AHC/AHCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V

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PHI

飞利浦

Dual D-type flip-flop with set and reset; positive-edge trigger

General description The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. Features ■ Balanced propagation delays ■ All inputs have Schmitt-trigger actions ■ Inputs accept

文件：110.24 Kbytes 页数：18 Pages

恩XP

Dual D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC74; 74AHCT74 is a dual positive-edge triggered, D-type flip-flop with individual data

文件：256.18 Kbytes 页数：15 Pages

NEXPERIA

安世

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74AHC/AHCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V

文件：92.28 Kbytes 页数：20 Pages

PHI

飞利浦

Dual D-type flip-flop with set and reset positive-edge trigger

General description The 74AHC74-Q100; 74AHCT74-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. Features and benefits ■ Automotive product qualification in accordance with AEC-Q100 (Gra

文件：752.8 Kbytes 页数：19 Pages

NEXPERIA

安世

Dual D-type flip-flop with set and reset; positive-edge trigger

The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.\n The 74AHC74; 74AHCT74 is a dual positive-edge triggered, D-type flip-flop with individual data inputs (D), clock inputs • Balanced propagation delays\n• All inputs have Schmitt-trigger actions\n• Inputs accept voltages higher than VCC\n• Input levels:• For 74AHC74: CMOS level\n• For 74AHCT74: TTL level\n\n• ESD protection:• HBM EIA/JESD22-A114E exceeds 2000 V\n• MM EIA/JESD22-A115-A exceeds 200 V\n• CDM EIA/JESD22-C1;

Nexperia

安世

Dual D-type flip-flop with set and reset; positive-edge trigger

The 74AHC74-Q100; 74AHCT74-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.\n The 74AHC74-Q100; 74AHCT74-Q100 is a dual positive-edge triggered, D-type flip-flop with individual data inpu • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Balanced propagation delays\n• All inputs have Schmitt-trigger actions\n• Inputs accept voltages higher than VCC\n• Input levels:• For 74AHC74-Q100: CMOS level\n•;

Nexperia

安世

Package：14-TSSOP（0.173"，4.40mm 宽）；包装：管件 功能：设置（预设）和复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE DUAL 1BIT 14TSSOP

Nexperia USA Inc.

Package：14-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 功能：设置（预设）和复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE DUAL 1BIT 14TSSOP

Nexperia USA Inc.

Package：14-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 功能：设置（预设）和复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE DUAL 1BIT 14TSSOP

Nexperia USA Inc.