8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

DESCRIPTION The 74AHC/AHCT595 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT595 is an 8-stage serial shift register with a storage register and 3-state outputs. The s

文件：103.31 Kbytes 页数：20 Pages

PHI

PHI

8-BIT SHIFT REGISTER WITH 8-BIT OUTPUT REGISTER

Description The 74AHC595 is an advanced high speed CMOS device. An eight bit shift register accepts data from the serial input (DS) on each positive transition of the shift register clock (STCP). When asserted low the reset function (MR) sets all shift register values to zero and is independ

文件：319.4 Kbytes 页数：10 Pages

DIODES

美台半导体

Advanced High Speed CMOS Logic

Features:  High Frequency: 110 MHz (Min) VCC = 5V, CL = 15pF  Output Drive Capability: 15 LSTTL Loads  Low Input Current: 0.1μA  Outputs directly interface CMOS, NMOS and TTL  CMOS High Noise Immunity  Function compatible with 74LS595  Performance upgrade for 74AC595, 74HC595  Exte

文件：2.14266 Mbytes 页数：8 Pages

SS

8-bit serial-in/serial-out or parallel-out shift register with output latches

1. General description The 74AHC595; 74AHCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading

文件：294.59 Kbytes 页数：19 Pages

NEXPERIA

安世

standard-logic

The 74AHC595 is an advanced high speed CMOS device. \nAn eight bit shift register accpets data from the serial input (DS) on each positive transition of the shift register clock (STCP). When asserted low the reset function /MR sets all shift register values to zero and is indepent of all clocks.\

Diodes

美台半导体

8-bit serial-in/serial-out or parallel-out shift register with output latches

1. General description The 74AHC595; 74AHCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading

文件：294.59 Kbytes 页数：19 Pages

NEXPERIA

安世

8-bit serial-in/serial-out or parallel-out shift register with output latches

1. General description The 74AHC595; 74AHCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading

文件：294.59 Kbytes 页数：19 Pages

NEXPERIA

安世

8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

DESCRIPTION The 74AHC/AHCT595 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT595 is an 8-stage serial shift register with a storage register and 3-state outputs. The s

文件：103.31 Kbytes 页数：20 Pages

PHI

PHI

8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

DESCRIPTION The 74AHC/AHCT595 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT595 is an 8-stage serial shift register with a storage register and 3-state outputs. The s

文件：103.31 Kbytes 页数：20 Pages

PHI

PHI

8-bit serial-in/serial-out or parallel-out shift register with output latches

1. General description The 74AHC595; 74AHCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading

文件：294.59 Kbytes 页数：19 Pages

NEXPERIA

安世