Single D-type flip-flop; positive-edge trigger

DESCRIPTION The 74AHC1G/AHCT1G79 is a high-speed Si-gate CMOS device. The 74AHC1G/AHCT1G79 provides a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one

文件：83.59 Kbytes 页数：12 Pages

PHI

PHI

Single D-type flip-flop; positive-edge trigger

General description 74AHC1G79 and 74AHCT1G79 are high-speed Si-gate CMOS devices. They provide a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up

文件：82.92 Kbytes 页数：12 Pages

恩XP

Single D-type flip-flop; positive-edge trigger

1. General description The 74AHC1G79; 74AHCT1G79 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Inputs are overvoltage tole

文件：218.22 Kbytes 页数：12 Pages

NEXPERIA

安世

Single D-type flip-flop; positive-edge trigger

文件：82.92 Kbytes 页数：12 Pages

恩XP

Single D-type flip-flop; positive-edge trigger

General description 74AHC1G79 and 74AHCT1G79 are high-speed Si-gate CMOS devices. They provide a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up

文件：82.92 Kbytes 页数：12 Pages

恩XP

丝印：A78；Package：SOT753；Single D-type flip-flop; positive-edge trigger

1. General description The 74AHC1G79; 74AHCT1G79 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Inputs are overvoltage tole

文件：218.22 Kbytes 页数：12 Pages

NEXPERIA

安世

丝印：A79；Package：SC-74A；Single D-type flip-flop; positive-edge trigger

1. General description The 74AHC1G79-Q100; 74AHCT1G79-Q100 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Inputs are overvo

文件：242.38 Kbytes 页数：13 Pages

NEXPERIA

安世

丝印：A79；Package：SC-74A；Single D-type flip-flop; positive-edge trigger

1. General description The 74AHC1G79-Q100; 74AHCT1G79-Q100 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Inputs are overvo

文件：218.37 Kbytes 页数：12 Pages

NEXPERIA

安世

丝印：AP；Package：SOT353-1；Single D-type flip-flop; positive-edge trigger

1. General description The 74AHC1G79; 74AHCT1G79 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Inputs are overvoltage tole

文件：218.22 Kbytes 页数：12 Pages

NEXPERIA

安世

Single D-type flip-flop; positive-edge trigger

General description 74AHC1G79 and 74AHCT1G79 are high-speed Si-gate CMOS devices. They provide a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up

文件：82.92 Kbytes 页数：12 Pages

恩XP