Quad 2-input NOR gate

General description The 74AHC02; 74AHCT02 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard JESD7-A. The 74AHC02; 74AHCT02 provides the quad 2-input NOR function. Features ■ Balanced propagation d

文件：94 Kbytes 页数：14 Pages

恩XP

Quad 2-input NOR gate

1. General description The 74AHC02; 74AHCT02 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC02; 74AHCT02 provides a quad 2-input NOR function. 2. Features and benefits • Balance

文件：225.55 Kbytes 页数：12 Pages

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Quad 2-input NOR gate

General description The 74AHC02; 74AHCT02 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard JESD7-A. The 74AHC02; 74AHCT02 provides the quad 2-input NOR function. Features ■ Balanced propagation d

文件：94 Kbytes 页数：14 Pages

恩XP

Quad 2-input NOR gate

DESCRIPTION The 74AHC/AHCT02 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT02 provides the Quad 2-input OR function. FEATURES • ESD protection: HBM EIA/JESD22-A114-

文件：74.48 Kbytes 页数：16 Pages

PHI

飞利浦

Quad 2-input NOR gate

General description The 74AHC02; 74AHCT02 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard JESD7-A. The 74AHC02; 74AHCT02 provides the quad 2-input NOR function. Features ■ Balanced propagation d

文件：84.42 Kbytes 页数：13 Pages

恩XP

Quad 2-input NOR gate

1. General description The 74AHC02; 74AHCT02 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC02; 74AHCT02 provides a quad 2-input NOR function. 2. Features and benefits • Balance

文件：225.55 Kbytes 页数：12 Pages

NEXPERIA

安世

Quad 2-input NOR gate

DESCRIPTION The 74AHC/AHCT02 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT02 provides the Quad 2-input OR function. FEATURES • ESD protection: HBM EIA/JESD22-A114-

文件：74.48 Kbytes 页数：16 Pages

PHI

飞利浦

Automotive product qualification in accordance with AEC-Q100

文件：717.71 Kbytes 页数：15 Pages

NEXPERIA

安世

Automotive product qualification in accordance with AEC-Q100

文件：717.71 Kbytes 页数：15 Pages

NEXPERIA

安世

Automotive product qualification in accordance with AEC-Q100

文件：717.71 Kbytes 页数：15 Pages

NEXPERIA

安世