Dual JK Positive Edge?뭈riggered Flip?묯lop

The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip−flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J

文件：233.33 Kbytes 页数：9 Pages

ONSEMI

安森美半导体

Dual JK Positive Edge-Triggered Flip-Flop

General Description The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecti

文件：100.04 Kbytes 页数：9 Pages

FAIRCHILD

仙童半导体

Dual JK Positive Edge-Triggered Flip-Flop

Features ■ ICC reduced by 50% ■ Outputs source/sink 24mA ■ ACT109 has TTL-compatible inputs General Description The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock wav

文件：349.95 Kbytes 页数：12 Pages

ONSEMI

安森美半导体

Dual JK Positive Edge-Triggered Flip-Flop

General Description The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecti

文件：100.04 Kbytes 页数：9 Pages

FAIRCHILD

仙童半导体

Dual JK Positive Edge-Triggered Flip-Flop

Features ■ ICC reduced by 50% ■ Outputs source/sink 24mA ■ ACT109 has TTL-compatible inputs General Description The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock wav

文件：349.95 Kbytes 页数：12 Pages

ONSEMI

安森美半导体

TRIPLE 3-INPUT NAND GATE

DESCRIPTION The 74ACT10 is an advanced high-speed CMOS TRIPLE 3-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology. The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output. The d

文件：67.36 Kbytes 页数：7 Pages

STMICROELECTRONICS

意法半导体

TRIPLE 3-INPUT NAND GATE

DESCRIPTION The 74ACT10 is an advanced high-speed CMOS TRIPLE 3-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology. The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output. The d

文件：67.36 Kbytes 页数：7 Pages

STMICROELECTRONICS

意法半导体

Triple 3-Input NAND Gate

General Description The AC/ACT10 contains three, 3-input NAND gates. Features ■ ICC reduced by 50 on 74AC only ■ Outputs source/sink 24mA

文件：84.65 Kbytes 页数：7 Pages

FAIRCHILD

仙童半导体

Triple 3-Input NAND Gate

General Description The AC/ACT10 contains three, 3-input NAND gates. Features ■ ICC reduced by 50 on 74AC only ■ Outputs source/sink 24mA

文件：84.65 Kbytes 页数：7 Pages

FAIRCHILD

仙童半导体

TRIPLE 3-INPUT AND GATE

DESCRIPTION The 74ACT11 is an advanced high-speed CMOS TRIPLE 3-INPUT AND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology. The internal circuit is composed of 4 stages including buffer output, which enables high noise immunity and stable output. The de

文件：67.25 Kbytes 页数：7 Pages

STMICROELECTRONICS

意法半导体