1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

文件：340.66 Kbytes 页数：13 Pages

RENESAS

瑞萨

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

文件：340.66 Kbytes 页数：13 Pages

RENESAS

瑞萨

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

文件：340.66 Kbytes 页数：13 Pages

RENESAS

瑞萨

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

文件：340.66 Kbytes 页数：13 Pages

RENESAS

瑞萨

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

文件：340.66 Kbytes 页数：13 Pages

RENESAS

瑞萨

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

文件：340.66 Kbytes 页数：13 Pages

RENESAS

瑞萨

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

文件：340.66 Kbytes 页数：13 Pages

RENESAS

瑞萨

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

文件：340.66 Kbytes 页数：13 Pages

RENESAS

瑞萨

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

文件：340.66 Kbytes 页数：13 Pages

RENESAS

瑞萨

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

文件：340.66 Kbytes 页数：13 Pages

RENESAS

瑞萨