WE-BAL Multilayer Chip Balun

General Information: Storage Conditions (in original packaging)

文件：938.87 Kbytes 页数：8 Pages

WURTHWurth Elektronik GmbH & Co. KG, Germany.

伍尔特伍尔特集团

WE-BAL Multilayer Chip Balun

It is recommended that the temperature of the component does not exceed +85°C under worst case conditions Storage Conditions (in original packaging)

文件：570.31 Kbytes 页数：7 Pages

WURTHWurth Elektronik GmbH & Co. KG, Germany.

伍尔特伍尔特集团

WE-BAL Multilayer Chip Balun

General Information: Storage Conditions (in original packaging)

文件：934.19 Kbytes 页数：8 Pages

WURTHWurth Elektronik GmbH & Co. KG, Germany.

伍尔特伍尔特集团

7/8 Diameter 5-Turn Wirewound Precision Potentiometer

SPECIAL FEATURES Center Tap Linearity Tape Rear Shaft Extension Flatted Shaft Slotted Shaft (Standard on single gang 7486 without RS) Shaft Lock (7481, 7486 only) High Torque 2–6 oz.-in. (7486 only) Additional Gangs Gold plated solder lug terminals (See optional

文件：78.46 Kbytes 页数：5 Pages

BITECH

7/8 Diameter 5-Turn Wirewound Precision Potentiometer

SPECIAL FEATURES Center Tap Linearity Tape Rear Shaft Extension Flatted Shaft Slotted Shaft (Standard on single gang 7486 without RS) Shaft Lock (7481, 7486 only) High Torque 2–6 oz.-in. (7486 only) Additional Gangs Gold plated solder lug terminals (See optional

文件：293.86 Kbytes 页数：4 Pages

BITECH

Quad 2-Input Exclusive-OR Gate

General Description This device contains four independent gates each of which performs the logic exclusive-OR function.

文件：34.5 Kbytes 页数：3 Pages

Fairchild

仙童半导体

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

文件：340.66 Kbytes 页数：13 Pages

RENESAS

瑞萨

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

文件：340.66 Kbytes 页数：13 Pages

RENESAS

瑞萨

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

文件：340.66 Kbytes 页数：13 Pages

RENESAS

瑞萨

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

文件：340.66 Kbytes 页数：13 Pages

RENESAS

瑞萨