CMOS SyncBiFIFOTM 64 x 36 x 2

• Free-running CLKA and CLKB can be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) • Two independent clocked FIFOs (64 x 36 storage capacity each) buffering data in opposite directions • Mailbox bypass Register for each FIFO • Progra

文件：611.36 Kbytes 页数：26 Pages

RENESAS

瑞萨

CMOS SyncBiFIFOTM 64 x 36 x 2

• Free-running CLKA and CLKB can be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) • Two independent clocked FIFOs (64 x 36 storage capacity each) buffering data in opposite directions • Mailbox bypass Register for each FIFO • Progra

文件：611.36 Kbytes 页数：26 Pages

RENESAS

瑞萨

CMOS SyncBiFIFOTM 64 x 36 x 2

• Free-running CLKA and CLKB can be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) • Two independent clocked FIFOs (64 x 36 storage capacity each) buffering data in opposite directions • Mailbox bypass Register for each FIFO • Progra

文件：611.36 Kbytes 页数：26 Pages

RENESAS

瑞萨

CMOS SyncBiFIFOTM 64 x 36 x 2

• Free-running CLKA and CLKB can be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) • Two independent clocked FIFOs (64 x 36 storage capacity each) buffering data in opposite directions • Mailbox bypass Register for each FIFO • Progra

文件：611.36 Kbytes 页数：26 Pages

RENESAS

瑞萨

CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36

• Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) • 64 x 36 storage capacity FIFO buffering data from Port A to Port B • Mailbox bypass registers in each direction • Dynamic Port B bus sizing of 36 bits (l

文件：591.66 Kbytes 页数：27 Pages

RENESAS

瑞萨

CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36

• Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) • 64 x 36 storage capacity FIFO buffering data from Port A to Port B • Mailbox bypass registers in each direction • Dynamic Port B bus sizing of 36 bits (l

文件：591.66 Kbytes 页数：27 Pages

RENESAS

瑞萨

CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36

• Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) • 64 x 36 storage capacity FIFO buffering data from Port A to Port B • Mailbox bypass registers in each direction • Dynamic Port B bus sizing of 36 bits (l

文件：591.66 Kbytes 页数：27 Pages

RENESAS

瑞萨

CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36

• Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) • 64 x 36 storage capacity FIFO buffering data from Port A to Port B • Mailbox bypass registers in each direction • Dynamic Port B bus sizing of 36 bits (l

文件：591.66 Kbytes 页数：27 Pages

RENESAS

瑞萨

CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36

• Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) • 64 x 36 storage capacity FIFO buffering data from Port A to Port B • Mailbox bypass registers in each direction • Dynamic Port B bus sizing of 36 bits (l

文件：591.66 Kbytes 页数：27 Pages

RENESAS

瑞萨

CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36

• Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) • 64 x 36 storage capacity FIFO buffering data from Port A to Port B • Mailbox bypass registers in each direction • Dynamic Port B bus sizing of 36 bits (l

文件：591.66 Kbytes 页数：27 Pages

RENESAS

瑞萨